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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra186-display.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) Display Hub
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display-hub@[0-9a-f]+$"
19 - nvidia,tegra186-display
20 - nvidia,tegra194-display
[all …]
Dnvidia,tegra186-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display@[0-9a-f]+$"
19 - nvidia,tegra186-dc
20 - nvidia,tegra194-dc
[all …]
Dnvidia,tegra124-sor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
19 pattern: "^sor@[0-9a-f]+$"
23 - enum:
24 - nvidia,tegra124-sor
25 - nvidia,tegra210-sor
[all …]
Dnvidia,tegra124-dpaux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
24 pattern: "^dpaux@[0-9a-f]+$"
28 - enum:
29 - nvidia,tegra124-dpaux
[all …]
Dnvidia,tegra124-vic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^vic@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra124-vic
21 - nvidia,tegra210-vic
[all …]
Dnvidia,tegra20-vi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^vi@[0-9a-f]+$"
19 - const: nvidia,tegra20-vi
20 - const: nvidia,tegra30-vi
21 - const: nvidia,tegra114-vi
[all …]
Dnvidia,tegra20-host1x.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The host1x top-level node defines a number of children, each
19 - enum:
20 - nvidia,tegra20-host1x
21 - nvidia,tegra30-host1x
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
[all …]
Dtegra194-p3509-0000+p3668-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra194-p3668-0000.dtsi"
11 compatible = "nvidia,p3509-0000+p3668-0000", "nvidia,tegra194";
17 dma-controller@2930000 {
21 interrupt-controller@2a40000 {
36 vcc-supply = <&vdd_1v8>;
37 address-width = <8>;
[all …]
Dtegra194-p2972-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra194-p2888.dtsi"
11 compatible = "nvidia,p2972-0000", "nvidia,tegra194";
17 dma-controller@2930000 {
21 interrupt-controller@2a40000 {
32 vcc-supply = <&vdd_1v8ls>;
33 address-width = <8>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
Dtegra194-p2972-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra194-p2888.dtsi"
11 compatible = "nvidia,p2972-0000", "nvidia,tegra194";
24 #address-cells = <1>;
25 #size-cells = <0>;
31 remote-endpoint = <&xbar_i2s1_ep>;
39 dai-format = "i2s";
[all …]
/kernel/linux/linux-6.6/drivers/iommu/arm/arm-smmu/
Darm-smmu-nvidia.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 NVIDIA CORPORATION. All rights reserved.
12 #include "arm-smmu.h"
15 * Tegra194 has three ARM MMU-500 Instances.
18 * non-isochronous HW devices.
23 * memory client. This is necessary to allow for use-case such as seamlessly
24 * handing over the display controller configuration from the firmware to the
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
69 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg()
90 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg64()
[all …]
/kernel/linux/linux-6.6/sound/pci/hda/
Dhda_tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
67 * Tegra194 does not reflect correct number of SDO lines. Below macro
93 "Automatic power-saving timeout (in seconds, 0 = disable).");
105 v = readl(hda->regs + HDA_IPFS_CONFIG); in hda_tegra_init()
107 writel(v, hda->regs + HDA_IPFS_CONFIG); in hda_tegra_init()
110 v = readl(hda->regs + HDA_CFG_CMD); in hda_tegra_init()
114 writel(v, hda->regs + HDA_CFG_CMD); in hda_tegra_init()
116 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); in hda_tegra_init()
117 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); in hda_tegra_init()
[all …]
Dpatch_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
90 bool chmap_set; /* channel-map override by ALSA API? */
91 unsigned char chmap[8]; /* ALSA API channel-map */
127 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */
176 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
178 * Non-generic VIA/NVIDIA specific
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/tegra/
Ddrm.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
27 #include <asm/dma-iommu.h>
76 struct drm_device *drm = old_state->dev; in tegra_atomic_commit_tail()
77 struct tegra_drm *tegra = drm->dev_private; in tegra_atomic_commit_tail()
79 if (tegra->hub) { in tegra_atomic_commit_tail()
108 return -ENOMEM; in tegra_drm_open()
110 idr_init_base(&fpriv->legacy_contexts, 1); in tegra_drm_open()
111 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1); in tegra_drm_open()
112 xa_init(&fpriv->syncpoints); in tegra_drm_open()
[all …]
Dhub.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
64 * The GPU sector layout is only supported on Tegra194, but these will
65 * be filtered out later on by ->format_mod_supported() on SoCs where
82 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
83 return plane->offset + offset; in tegra_plane_offset()
87 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
88 return plane->offset + offset; in tegra_plane_offset()
92 offset = 0x1c0 + (offset - 0x800); in tegra_plane_offset()
93 return plane->offset + offset; in tegra_plane_offset()
[all …]
Ddpaux.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pinctrl/pinconf-generic.h>
21 #include <drm/display/drm_dp_helper.h>
22 #include <drm/display/drm_dp_aux_bus.h>
79 u32 value = readl(dpaux->regs + (offset << 2)); in tegra_dpaux_readl()
81 trace_dpaux_readl(dpaux->dev, offset, value); in tegra_dpaux_readl()
89 trace_dpaux_writel(dpaux->dev, offset, value); in tegra_dpaux_writel()
90 writel(value, dpaux->regs + (offset << 2)); in tegra_dpaux_writel()
99 size_t num = min_t(size_t, size - i * 4, 4); in tegra_dpaux_write_fifo()
115 size_t num = min_t(size_t, size - i * 4, 4); in tegra_dpaux_read_fifo()
[all …]
Ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
43 stats->frames = 0; in tegra_dc_stats_reset()
44 stats->vblank = 0; in tegra_dc_stats_reset()
45 stats->underflow = 0; in tegra_dc_stats_reset()
46 stats->overflow = 0; in tegra_dc_stats_reset()
65 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
66 return plane->offset + offset; in tegra_plane_offset()
70 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
71 return plane->offset + offset; in tegra_plane_offset()
[all …]
Dsor.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
19 #include <drm/display/drm_dp_helper.h>
20 #include <drm/display/drm_scdc_helper.h>
486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
504 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
Ddrm.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
64 struct drm_device *drm = old_state->dev; in tegra_atomic_commit_tail()
65 struct tegra_drm *tegra = drm->dev_private; in tegra_atomic_commit_tail()
67 if (tegra->hub) { in tegra_atomic_commit_tail()
91 return -ENOMEM; in tegra_drm_open()
93 idr_init_base(&fpriv->contexts, 1); in tegra_drm_open()
94 mutex_init(&fpriv->lock); in tegra_drm_open()
95 filp->driver_priv = fpriv; in tegra_drm_open()
102 context->client->ops->close_channel(context); in tegra_drm_context_free()
[all …]
Dhub.c1 // SPDX-License-Identifier: GPL-2.0-only
65 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
66 return plane->offset + offset; in tegra_plane_offset()
70 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
71 return plane->offset + offset; in tegra_plane_offset()
75 offset = 0x1c0 + (offset - 0x800); in tegra_plane_offset()
76 return plane->offset + offset; in tegra_plane_offset()
79 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
81 return plane->offset + offset; in tegra_plane_offset()
87 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
[all …]
Ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
36 stats->frames = 0; in tegra_dc_stats_reset()
37 stats->vblank = 0; in tegra_dc_stats_reset()
38 stats->underflow = 0; in tegra_dc_stats_reset()
39 stats->overflow = 0; in tegra_dc_stats_reset()
58 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
59 return plane->offset + offset; in tegra_plane_offset()
63 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
64 return plane->offset + offset; in tegra_plane_offset()
68 offset = 0x1c0 + (offset - 0x800); in tegra_plane_offset()
[all …]
/kernel/linux/linux-6.6/drivers/dma/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
154 tristate "SA-11x0 DMA support"
159 Support the DMA engine found on Intel StrongARM SA-1100 and
160 SA-1110 SoCs. This DMA engine can only be used with on-chip
220 This module can be found on Freescale Vybrid and LS-1 SoCs.
263 Enable support for the IMG multi-threaded DMA controller (MDC).
283 tristate "Intel integrated DMA 64-bit support"
319 accel-config) to continue function. It is expected that accel-config
[all …]
/kernel/linux/linux-5.10/sound/pci/hda/
Dpatch_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
77 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
78 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
84 bool chmap_set; /* channel-map override by ALSA API? */
85 unsigned char chmap[8]; /* ALSA API channel-map */
163 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
165 * Non-generic VIA/NVIDIA specific
186 struct hdmi_spec *spec = codec->spec; in codec_has_acomp()
[all …]

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