| /kernel/linux/linux-5.10/drivers/gpu/drm/tegra/ |
| D | mipi-phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "mipi-phy.h"
12 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
13 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/tegra/ |
| D | mipi-phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "mipi-phy.h"
12 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
13 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
18 v = (tmax - tmin) * percent; in linear_inter()
20 if (even && (v & 0x1)) in linear_inter()
21 return max_t(s32, min_result, v - 1); in linear_inter()
26 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
34 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
37 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true); in dsi_dphy_timing_calc_clk_zero()
40 clk_z = linear_inter(tmax, tmin, pcnt, 0, true); in dsi_dphy_timing_calc_clk_zero()
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| D | dsi_phy_14nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
14 struct msm_dsi_dphy_timing *timing, in dsi_14nm_dphy_set_timing() argument
17 void __iomem *base = phy->lane_base; in dsi_14nm_dphy_set_timing()
19 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero; in dsi_14nm_dphy_set_timing()
20 u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare; in dsi_14nm_dphy_set_timing()
21 u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail; in dsi_14nm_dphy_set_timing()
22 u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst; in dsi_14nm_dphy_set_timing()
23 u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly; in dsi_14nm_dphy_set_timing()
24 u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : in dsi_14nm_dphy_set_timing()
25 timing->hs_halfbyte_en; in dsi_14nm_dphy_set_timing()
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| D | dsi_phy_20nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
12 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing()
15 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
17 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_20nm_dphy_set_timing()
19 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_20nm_dphy_set_timing()
20 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
26 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
28 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_20nm_dphy_set_timing()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
8 #include <dt-bindings/phy/phy.h>
13 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
20 v = (tmax - tmin) * percent; in linear_inter()
22 if (even && (v & 0x1)) in linear_inter()
23 return max_t(s32, min_result, v - 1); in linear_inter()
28 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
35 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
36 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
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| D | dsi_phy_20nm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
13 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing()
16 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
18 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_20nm_dphy_set_timing()
20 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
25 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
27 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
29 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_20nm_dphy_set_timing()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
28 #define CLK_SOURCE_EMC 0x19c
30 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
31 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
36 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
47 * When we change the timing to a timing with a parent that has the same
49 * timing that has a different clock source.
52 #define EMC_SRC_PLL_M 0
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| /kernel/linux/linux-6.6/drivers/clk/tegra/ |
| D | clk-tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
29 #define CLK_SOURCE_EMC 0x19c
31 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
32 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
37 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
48 * When we change the timing to a timing with a parent that has the same
50 * timing that has a different clock source.
53 #define EMC_SRC_PLL_M 0
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/link/ |
| D | link_validation.c | 27 * This file owns timing validation against various link limitations. (ex.
38 static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing) in get_tmds_output_pixel_clock_100hz() argument
41 uint32_t pxl_clk = timing->pix_clk_100hz; in get_tmds_output_pixel_clock_100hz()
43 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in get_tmds_output_pixel_clock_100hz()
45 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in get_tmds_output_pixel_clock_100hz()
48 if (timing->display_color_depth == COLOR_DEPTH_101010) in get_tmds_output_pixel_clock_100hz()
50 else if (timing->display_color_depth == COLOR_DEPTH_121212) in get_tmds_output_pixel_clock_100hz()
57 const struct dc_crtc_timing *timing, in dp_active_dongle_validate_timing() argument
60 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps; in dp_active_dongle_validate_timing()
62 switch (dpcd_caps->dongle_type) { in dp_active_dongle_validate_timing()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | timing.c | 26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
45 case 0x10: in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | timing.c | 26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
45 case 0x10: in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
[all …]
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| /kernel/linux/linux-5.10/drivers/memory/tegra/ |
| D | tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
25 #define EMC_FBIO_CFG5 0x104
26 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
27 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
29 #define EMC_INTSTATUS 0x0
32 #define EMC_CFG 0xc
37 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
40 #define EMC_REFCTRL 0x20
41 #define EMC_REFCTRL_DEV_SEL_SHIFT 0
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_encoder_phys_vid.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
17 (e) && (e)->parent ? \
18 (e)->parent->base.id : -1, \
19 (e) && (e)->hw_intf ? \
20 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
23 (e) && (e)->parent ? \
24 (e)->parent->base.id : -1, \
25 (e) && (e)->hw_intf ? \
26 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
[all …]
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| /kernel/linux/linux-5.10/drivers/devfreq/ |
| D | rk3399_dmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Lin Huang <hl@rock-chips.com>
7 #include <linux/arm-smccc.h>
11 #include <linux/devfreq-event.h>
65 struct dram_timing timing; member
79 unsigned long old_clk_rate = dmcfreq->rate; in rk3399_dmcfreq_target()
93 if (dmcfreq->rate == target_rate) in rk3399_dmcfreq_target()
94 return 0; in rk3399_dmcfreq_target()
96 mutex_lock(&dmcfreq->lock); in rk3399_dmcfreq_target()
98 if (dmcfreq->regmap_pmu) { in rk3399_dmcfreq_target()
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/ |
| D | gbefb.c | 4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
37 struct gbe_timing_info timing; member
42 #define GBE_BASE 0x16000000 /* SGI O2 */
44 /* macro for fastest write-though access to the framebuffer */
63 #define TILE_MASK (TILE_SIZE - 1)
81 static int gbe_turned_on; /* 0 turned off, 1 turned on */
87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
92 .xoffset = 0,
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| /kernel/linux/linux-6.6/drivers/video/fbdev/ |
| D | gbefb.c | 4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
37 struct gbe_timing_info timing; member
42 #define GBE_BASE 0x16000000 /* SGI O2 */
44 /* macro for fastest write-though access to the framebuffer */
63 #define TILE_MASK (TILE_SIZE - 1)
81 static int gbe_turned_on; /* 0 turned off, 1 turned on */
87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
92 .xoffset = 0,
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| /kernel/linux/linux-5.10/drivers/video/fbdev/via/ |
| D | via_modesetting.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
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| /kernel/linux/linux-6.6/drivers/video/fbdev/via/ |
| D | via_modesetting.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_optc.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
32 optc1->tg_regs->reg
35 optc1->base.ctx
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
42 bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) in optc201_is_two_pixels_per_containter() argument
44 return optc1_is_two_pixels_per_containter(timing); in optc201_is_two_pixels_per_containter()
51 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc201_triplebuffer_lock()
52 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); in optc201_triplebuffer_lock()
53 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc201_triplebuffer_lock()
55 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_lock()
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| /kernel/linux/linux-6.6/drivers/memory/tegra/ |
| D | tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
31 #define EMC_FBIO_CFG5 0x104
32 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
33 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
36 #define EMC_INTSTATUS 0x0
39 #define EMC_CFG 0xc
44 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
47 #define EMC_REFCTRL 0x20
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_encoder_phys_vid.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
13 (e) && (e)->parent ? \
14 (e)->parent->base.id : -1, \
15 (e) && (e)->hw_intf ? \
16 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
19 (e) && (e)->parent ? \
20 (e)->parent->base.id : -1, \
21 (e) && (e)->hw_intf ? \
22 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/sti/ |
| D | sti_awg_utils.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
14 #define AWG_MAX_ARG 0x3ff
34 u32 instruction = 0; in awg_generate_instr()
35 u32 mux = (mux_sel << 8) & 0x1ff; in awg_generate_instr()
36 u32 data_enable = (data_en << 9) & 0x2ff; in awg_generate_instr()
46 while (arg_tmp > 0) { in awg_generate_instr()
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/sti/ |
| D | sti_awg_utils.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
14 #define AWG_MAX_ARG 0x3ff
34 u32 instruction = 0; in awg_generate_instr()
35 u32 mux = (mux_sel << 8) & 0x1ff; in awg_generate_instr()
36 u32 data_enable = (data_en << 9) & 0x2ff; in awg_generate_instr()
46 while (arg_tmp > 0) { in awg_generate_instr()
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dsc/ |
| D | dc_dsc.c | 52 /* Need to account for padding due to pixel-to-symbol packing
56 const struct dc_crtc_timing *timing, const uint32_t kbps) in apply_128b_132b_stream_overhead() argument
63 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
68 bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10); in apply_128b_132b_stream_overhead()
70 /* Symbols_per_HActive = HActive * bpp / (4 lanes * 32-bit symbol size) in apply_128b_132b_stream_overhead()
73 overhead_factor = dc_fixpt_from_int(timing->h_addressable); in apply_128b_132b_stream_overhead()
88 const struct dc_crtc_timing *timing, in dc_bandwidth_in_kbps_from_timing() argument
91 uint32_t bits_per_channel = 0; in dc_bandwidth_in_kbps_from_timing()
94 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
95 return dc_dsc_stream_bandwidth_in_kbps(timing, in dc_bandwidth_in_kbps_from_timing()
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