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/kernel/linux/linux-5.10/include/linux/dma/
Dsprd-dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
19 * trigger the destination channel's transaction automatically by hardware
22 * To support 2-stage tansfer, we must configure the channel mode and trigger
27 * enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
29 * support the 2-stage transfer.
35 * Now the DMA controller can supports 2 groups 2-stage transfer.
46 * enum sprd_dma_trg_mode: define the DMA channel trigger mode for 2-stage
48 * @SPRD_DMA_NO_TRG: No trigger setting.
49 * @SPRD_DMA_FRAG_DONE_TRG: Trigger the transaction of destination channel
[all …]
/kernel/linux/linux-6.6/include/linux/dma/
Dsprd-dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
19 * trigger the destination channel's transaction automatically by hardware
22 * To support 2-stage tansfer, we must configure the channel mode and trigger
27 * enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
29 * support the 2-stage transfer.
35 * Now the DMA controller can supports 2 groups 2-stage transfer.
46 * enum sprd_dma_trg_mode: define the DMA channel trigger mode for 2-stage
48 * @SPRD_DMA_NO_TRG: No trigger setting.
49 * @SPRD_DMA_FRAG_DONE_TRG: Trigger the transaction of destination channel
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Domap5-uevm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
7 #include "omap5-board-common.dtsi"
11 compatible = "ti,omap5-uevm", "ti,omap5";
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
23 dsp_memory_region: dsp-memory@95000000 {
24 compatible = "shared-dma-pool";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Domap5-uevm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
7 #include "omap5-board-common.dtsi"
11 compatible = "ti,omap5-uevm", "ti,omap5";
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
23 dsp_memory_region: dsp-memory@95000000 {
24 compatible = "shared-dma-pool";
[all …]
Dkirkwood-l-50.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Check Point L-50 Board Description
7 /dts-v1/;
10 #include "kirkwood-6281.dtsi"
13 model = "Check Point L-50";
14 compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood";
23 stdout-path = &uart0;
27 pinctrl: pin-controller@10000 {
28 pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;
29 pinctrl-names = "default";
[all …]
Dbcm53573.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&gic>;
21 stdout-path = "serial0:115200n8";
25 #address-cells = <1>;
[all …]
Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
13 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
19 output hardware trigger signals. CTIs can have a maximum number of input and
20 output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
30 In general the connections between CTI and components via the trigger signals
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Dcoresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
13 a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
20 output hardware trigger signals. CTIs can have a maximum number of input and
21 output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
31 In general the connections between CTI and components via the trigger signals
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mfd/
Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers bindings
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm47081-luxul-xwr-1200.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
9 #include "bcm5301x-nand-cs0-bch4.dtsi"
12 compatible = "luxul,xwr-1200-v1", "brcm,bcm47081", "brcm,bcm4708";
13 model = "Luxul XWR-1200 V1";
29 #nvmem-cell-cells = <1>;
34 compatible = "gpio-leds";
36 led-power {
39 linux,default-trigger = "default-on";
42 led-lan3 {
[all …]
Dbcm47094-luxul-xwr-3150-v1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
9 #include "bcm5301x-nand-cs0-bch8.dtsi"
12 compatible = "luxul,xwr-3150-v1", "brcm,bcm47094", "brcm,bcm4708";
13 model = "Luxul XWR-3150 V1";
30 #nvmem-cell-cells = <1>;
35 compatible = "gpio-leds";
37 led-power {
40 linux,default-trigger = "default-on";
43 led-usb3 {
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/fw/api/
Ddbg-tlv.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2018-2022 Intel Corporation
34 * struct iwl_fw_ini_header - Common Header for all ini debug TLV's structures
46 * struct iwl_fw_ini_region_dev_addr - Configuration to read device addresses
49 * @offset: offset to add to the base address of each chunk
57 * struct iwl_fw_ini_region_fifos - Configuration to read Tx/Rx fifos
70 * struct iwl_fw_ini_region_err_table - error table region data
75 * @base_addr: base address of the error table
87 * struct iwl_fw_ini_region_special_device_memory - special device memory
93 * @base_addr: base address of the error table
[all …]
/kernel/linux/linux-6.6/drivers/net/phy/
Ddp83640_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
20 #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
21 #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
26 #define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */
57 #define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */
59 #define TRIG_DIS (1<<9) /* Disable PTP Trigger */
60 #define TRIG_EN (1<<8) /* Enable PTP Trigger */
61 #define TRIG_READ (1<<7) /* Read PTP Trigger */
62 #define TRIG_LOAD (1<<6) /* Load PTP Trigger */
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Ddp83640_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
20 #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
21 #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
26 #define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */
57 #define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */
59 #define TRIG_DIS (1<<9) /* Disable PTP Trigger */
60 #define TRIG_EN (1<<8) /* Enable PTP Trigger */
61 #define TRIG_READ (1<<7) /* Read PTP Trigger */
62 #define TRIG_LOAD (1<<6) /* Load PTP Trigger */
[all …]
/kernel/linux/linux-6.6/Documentation/firmware-guide/acpi/apei/
Deinj.rst1 .. SPDX-License-Identifier: GPL-2.0
15 which shows that the BIOS is exposing an EINJ table - it is the
39 - available_error_type
47 0x00000002 Processor Uncorrectable non-fatal
50 0x00000010 Memory Uncorrectable non-fatal
53 0x00000080 PCI Express Uncorrectable non-fatal
56 0x00000400 Platform Uncorrectable non-fatal
63 - error_type
68 - error_inject
70 Write any integer to this file to trigger the error injection. Make
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdkfd/
Dkfd_smi_events.h1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
33 unsigned long address, bool write_fault,
36 unsigned long address, bool migration);
41 uint32_t trigger);
44 uint32_t from, uint32_t to, uint32_t trigger);
46 uint32_t trigger);
50 unsigned long address, unsigned long last,
51 uint32_t trigger);
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Dkirkwood-l-50.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Check Point L-50 Board Description
7 /dts-v1/;
10 #include "kirkwood-6281.dtsi"
13 model = "Check Point L-50";
14 compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood";
23 stdout-path = &uart0;
27 pinctrl: pin-controller@10000 {
28 pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;
29 pinctrl-names = "default";
[all …]
/kernel/liteos_m/arch/risc-v/nuclei/gcc/nmsis/Core/Include/
Dcore_feature_eclic.h4 * SPDX-License-Identifier: Apache-2.0
10 * www.apache.org/licenses/LICENSE-2.0
29 * 2. __ECLIC_BASEADDR: Base address of the ECLIC unit.
31 * Valid number is 1 - 8.
122 #define ECLIC_NON_VECTOR_INTERRUPT 0x0 /*!< Non-Ve…
125 /**\brief ECLIC Trigger Enum for different Trigger Type */
130 ECLIC_MAX_TRIGGER = 0x3 /*!< MAX Supported Trigger Mode */
134 /* Base address of ECLIC(__ECLIC_BASEADDR) should be defined in <Device.h> */
139 /* Define __ECLIC_INTCTLBITS to get via ECLIC->INFO if not defined */
144 …ASE __ECLIC_BASEADDR /*!< ECLIC Base Address */
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/fw/
Derror-dump.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2014-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
17 * enum iwl_fw_error_dump_type - types of data in the dump file
18 * @IWL_FW_ERROR_DUMP_CSR: Control Status Registers - from offset 0
25 * @IWL_FW_ERROR_DUMP_PRPH: range of periphery registers - there can be several
37 * for that reason is not in use in any other place in the Linux Wi-Fi
67 * struct iwl_fw_error_dump_data - data for one type
79 * struct iwl_dump_file_name_info - data for dump file name addition
[all …]
/kernel/linux/linux-6.6/arch/x86/kernel/acpi/
Dboot.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * boot.c - Architecture-Specific Low-Level ACPI Boot Support
22 #include <linux/efi-bgrt.h>
70 /* Physical address of the Multiprocessor Wakeup Structure mailbox */
72 /* Virtual address of the Multiprocessor Wakeup Structure mailbox */
80 * ->device_hotplug_lock
81 * ->acpi_ioapic_lock
82 * ->ioapic_lock
84 * ->acpi_ioapic_lock
85 * ->ioapic_mutex
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dcadence-quadspi.txt4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
9 physical address and length. The first entry is the address and
11 address and length of the QSPI Controller data area.
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/broadcom/bcmbca/
Dbcm4906-netgear-r8000p.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
19 compatible = "gpio-leds";
21 led-power-white {
27 led-power-amber {
33 led-wps {
39 led-2ghz {
45 led-5ghz-1 {
[all …]

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