Home
last modified time | relevance | path

Searched +full:tx0 +full:- +full:3 (Results 1 – 25 of 153) sorted by relevance

1234567

/kernel/linux/linux-6.6/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md Danish Anwar <danishanwar@ti.com>
13 Ethernet based on the Programmable Real-Time Unit and Industrial
17 - $ref: /schemas/remoteproc/ti,pru-consumer.yaml#
22 - ti,am654-icssg-prueth # for AM65x SoC family
32 dma-names:
34 - const: tx0-0
[all …]
Dti,k3-am654-cpsw-nuss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
22 Complex (UDMA-P) controller.
31 IEEE P902.3br/D2.0 Interspersing Express Traffic
52 "#address-cells": true
53 "#size-cells": true
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/can/
Dsja1000.txt5 - compatible : should be one of "nxp,sja1000", "technologic,sja1000".
7 - reg : should specify the chip select, address offset and size required
10 - interrupts: property with a value describing the interrupt source
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
20 - nxp,external-clock-frequency : Frequency of the external oscillator
25 - nxp,tx-output-mode : operation mode of the TX output control logic:
26 <0x0> : bi-phase output mode
31 - nxp,tx-output-config : TX output pin configuration:
32 <0x01> : TX0 invert
33 <0x02> : TX0 pull-down (default)
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/can/
Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
[all …]
/kernel/linux/linux-6.6/drivers/phy/qualcomm/
Dphy-qcom-edp.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
22 #include <dt-bindings/phy/phy.h>
24 #include "phy-qcom-qmp.h"
88 void __iomem *tx0; member
176 const struct qcom_edp_cfg *cfg = edp->cfg; in qcom_edp_phy_init()
180 ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); in qcom_edp_phy_init()
184 ret = clk_bulk_prepare_enable(ARRAY_SIZE(edp->clks), edp->clks); in qcom_edp_phy_init()
190 edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
193 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); in qcom_edp_phy_init()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/media/
Damphion,vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ming Qian <ming.qian@nxp.com>
12 - Shijie Qin <shijie.qin@nxp.com>
14 description: |-
20 pattern: "^vpu@[0-9a-f]+$"
24 - enum:
25 - nxp,imx8qm-vpu
26 - nxp,imx8qxp-vpu
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dnvidia,tegra30-ahub.txt4 - compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
5 must contain "nvidia,tegra114-ahub". For Tegra124, must contain
6 "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
8 - reg : Should contain the register physical address and length for each of
10 - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
11 - Tegra114 requires an additional entry, for the APBIF2 register block.
12 - interrupts : Should contain AHUB interrupt
13 - clocks : Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names : Must include the following entries:
[all …]
Dfsl,spdif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
20 - fsl,imx35-spdif
21 - fsl,vf610-spdif
22 - fsl,imx6sx-spdif
32 - description: DMA controller phandle and request line for RX
33 - description: DMA controller phandle and request line for TX
35 dma-names:
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
Dnvidia,tegra30-ahub.txt4 - compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
5 must contain "nvidia,tegra114-ahub". For Tegra124, must contain
6 "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
8 - reg : Should contain the register physical address and length for each of
10 - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
11 - Tegra114 requires an additional entry, for the APBIF2 register block.
12 - interrupts : Should contain AHUB interrupt
13 - clocks : Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names : Must include the following entries:
[all …]
Drenesas,rz-ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 - $ref: dai-common.yaml#
18 - enum:
19 - renesas,r9a07g043-ssi # RZ/G2UL
20 - renesas,r9a07g044-ssi # RZ/G2{L,LC}
[all …]
Dfsl,spdif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
20 - fsl,imx35-spdif
21 - fsl,vf610-spdif
22 - fsl,imx6sx-spdif
23 - fsl,imx8qm-spdif
24 - fsl,imx8qxp-spdif
25 - fsl,imx8mq-spdif
[all …]
/kernel/linux/linux-5.10/include/sound/
Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 #define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */
27 #define AK4114_REG_TXCSB3 0x10 /* TX channel status byte 3 */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
[all …]
/kernel/linux/linux-6.6/include/sound/
Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 #define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */
27 #define AK4114_REG_TXCSB3 0x10 /* TX channel status byte 3 */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
[all …]
/kernel/linux/linux-6.6/arch/x86/crypto/
Dtwofish-x86_64-asm_64-3way.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Twofish Cipher 3-way parallel algorithm (x86_64)
10 .file "twofish-x86_64-asm-3way.S"
22 3-way twofish
93 #define g1g2_3(ab, cd, Tx0, Tx1, Tx2, Tx3, Ty0, Ty1, Ty2, Ty3, x, y) \ argument
95 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 0, ab ## 0, x ## 0); \
98 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 1, ab ## 1, x ## 1); \
101 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 2, ab ## 2, x ## 2); \
243 encrypt_cycle3(RAB, CD, 3);
291 decrypt_cycle3(RAB, CD, 3);
/kernel/linux/linux-5.10/arch/x86/crypto/
Dtwofish-x86_64-asm_64-3way.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Twofish Cipher 3-way parallel algorithm (x86_64)
10 .file "twofish-x86_64-asm-3way.S"
22 3-way twofish
93 #define g1g2_3(ab, cd, Tx0, Tx1, Tx2, Tx3, Ty0, Ty1, Ty2, Ty3, x, y) \ argument
95 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 0, ab ## 0, x ## 0); \
98 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 1, ab ## 1, x ## 1); \
101 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 2, ab ## 2, x ## 2); \
243 encrypt_cycle3(RAB, CD, 3);
291 decrypt_cycle3(RAB, CD, 3);
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/freescale/
Dfsl,scu.txt2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
35 Channel 0 must be "tx0" or "rx0".
38 Channel 3 must be "tx3" or "rx3".
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dti,k3-am654-cpsw-nuss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
16 CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),
25 Peripheral Root Complex (UDMA-P) controller.
34 IEEE P902.3br/D2.0 Interspersing Express Traffic
47 "#address-cells": true
[all …]
/kernel/linux/linux-5.10/Documentation/driver-api/dmaengine/
Dpxa_dma.rst2 PXA/MMP - DMA Slave controller
22 at the time of irq/dma tx2 is already finished, tx1->complete() and
23 tx2->complete() should be called.
36 A driver should be able to request a priority, especially the real-time
46 b) Transfer anatomy for a scatter-gather transfer
50 +------------+-----+---------------+----------------+-----------------+
51 | desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker |
52 +------------+-----+---------------+----------------+-----------------+
54 This structure is pointed by dma->sg_cpu.
57 - desc-sg[i]: i-th descriptor, transferring the i-th sg
[all …]
/kernel/linux/linux-6.6/Documentation/driver-api/dmaengine/
Dpxa_dma.rst2 PXA/MMP - DMA Slave controller
22 at the time of irq/dma tx2 is already finished, tx1->complete() and
23 tx2->complete() should be called.
36 A driver should be able to request a priority, especially the real-time
46 b) Transfer anatomy for a scatter-gather transfer
50 +------------+-----+---------------+----------------+-----------------+
51 | desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker |
52 +------------+-----+---------------+----------------+-----------------+
54 This structure is pointed by dma->sg_cpu.
57 - desc-sg[i]: i-th descriptor, transferring the i-th sg
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/rockchip/
Drk3588s-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
15 /omit-if-no-ref/
16 auddsm_pins: auddsm-pins {
19 <3 RK_PA1 4 &pcfg_pull_none>,
21 <3 RK_PA2 4 &pcfg_pull_none>,
23 <3 RK_PA3 4 &pcfg_pull_none>,
25 <3 RK_PA4 4 &pcfg_pull_none>;
30 /omit-if-no-ref/
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Domap-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/omap-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Aswath Govindraju <a-govindraju@ti.com>
13 - $ref: spi-controller.yaml#
18 - items:
19 - enum:
20 - ti,am654-mcspi
21 - ti,am4372-mcspi
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Domap2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/omap.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Domap2.dtsi4 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/omap.h>
18 interrupt-parent = <&intc>;
19 #address-cells = <1>;
20 #size-cells = <1>;
32 #address-cells = <0>;
33 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap1/
Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP1/OMAP7xx - specific DMA driver
5 * Copyright (C) 2003 - 2008 Nokia Corporation
10 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
15 * - G, Manjunath Kondaiah <manjugk@ti.com>
24 #include <linux/dma-mapping.h>
26 #include <linux/omap-dma.h>
82 .end = OMAP1_DMA_BASE + SZ_2K - 1,
[all …]

1234567