Home
last modified time | relevance | path

Searched +full:v2m +full:- +full:memory +full:- +full:map (Results 1 – 25 of 41) sorted by relevance

12

/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dvexpress-v2m-rs1.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * V2M-P1
8 * HBI-0190D
10 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
14 * original variant (vexpress-v2m.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m.dtsi!
22 v2m_fixed_3v3: fixed-regulator-0 {
23 compatible = "regulator-fixed";
24 regulator-name = "3V3";
25 regulator-min-microvolt = <3300000>;
[all …]
Dvexpress-v2m.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * V2M-P1
8 * HBI-0190D
10 * Original memory map ("Legacy memory map" in the board's
14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
24 model = "V2M-P1";
27 compatible = "arm,vexpress,v2m-p1", "simple-bus";
28 #address-cells = <2>; /* SMB chipselect number and offset */
29 #size-cells = <1>;
[all …]
Dxenvm-4.2.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
10 /dts-v1/;
13 model = "XENVM-4.2";
14 compatible = "xen,xenvm-4.2", "xen,xenvm";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/
Dvexpress-v2m-rs1.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * V2M-P1
8 * HBI-0190D
10 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
14 * original variant (vexpress-v2m.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m.dtsi!
22 v2m_fixed_3v3: fixed-regulator-0 {
23 compatible = "regulator-fixed";
24 regulator-name = "3V3";
25 regulator-min-microvolt = <3300000>;
[all …]
Dfoundation-v8.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Foundation-v8A";
16 compatible = "arm,foundation-aarch64", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
31 #address-cells = <2>;
32 #size-cells = <0>;
[all …]
Drtsm_ve-motherboard-rs2.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * "rs2" extension for the v2m motherboard
9 motherboard-bus {
10 arm,v2m-memory-map = "rs2";
12 iofpga-bus@300000000 {
13 virtio-p9@140000 {
19 virtio-net@150000 {
Drtsm_ve-motherboard.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
15 clock-output-names = "v2m:clk24mhz";
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <1000000>;
22 clock-output-names = "v2m:refclk1mhz";
26 compatible = "fixed-clock";
[all …]
Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
30 interrupt-names = "mhu_lpri_rx",
32 #mbox-cells = <1>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/arm/
Dvexpress-v2m.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * V2M-P1
8 * HBI-0190D
10 * Original memory map ("Legacy memory map" in the board's
14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <1>;
[all …]
Dvexpress-v2m-rs1.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * V2M-P1
8 * HBI-0190D
10 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
14 * original variant (vexpress-v2m.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m.dtsi!
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 v2m_fixed_3v3: fixed-regulator-0 {
24 compatible = "regulator-fixed";
25 regulator-name = "3V3";
[all …]
Dvexpress-v2p-ca5s.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
25 two different configurations ("memory maps"), care must be taken to include
37 further subvariants are released of the core tile, even more fine-granular
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
25 two different configurations ("memory maps"), care must be taken to include
37 further subvariants are released of the core tile, even more fine-granular
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/apm/
Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/apm/
Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dipq5332.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 sleep_clk: sleep-clk {
19 compatible = "fixed-clock";
[all …]
Dipq5018.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 sleep_clk: sleep-clk {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
Dipq9574.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/arm/
Drtsm_ve-motherboard-rs2.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * "rs2" extension for the v2m motherboard
9 motherboard-bus@8000000 {
10 arm,v2m-memory-map = "rs2";
12 iofpga-bus@300000000 {
Dfoundation-v8.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Foundation-v8A";
16 compatible = "arm,foundation-aarch64", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
31 #address-cells = <2>;
32 #size-cells = <0>;
[all …]
Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
31 #mbox-cells = <1>;
33 clock-names = "apb_pclk";
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/marvell/
Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/xen/
Dxenvm-4.2.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15 MPCore (V2P-CA15)
10 /dts-v1/;
13 model = "XENVM-4.2";
14 compatible = "xen,xenvm-4.2", "xen,xenvm";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amd/
Damd-seattle-soc.dtsi1 // SPDX-License-Identifier: GPL-2.0
10 interrupt-parent = <&gic0>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 gic0: interrupt-controller@e1101000 {
15 compatible = "arm,gic-400", "arm,cortex-a15-gic";
16 interrupt-controller;
17 #interrupt-cells = <3>;
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]

12