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Searched full:vs1 (Results 1 – 12 of 12) sorted by relevance

/arkcompiler/runtime_core/static_core/tests/cts-assembly/
Darrays-02.pa21 # - sig: starr vs1, vs2
Darrays-04.pa31 # - sig: fstarr.32 vs1, vs2
Darrays-03.pa31 # - sig: fstarr.64 vs1, vs2
Darrays-06.pa30 # - sig: starr vs1, vs2
/arkcompiler/runtime_core/tests/cts-assembly/
Darrays-02.pa21 # - sig: starr vs1, vs2
Darrays-04.pa31 # - sig: fstarr.32 vs1, vs2
Darrays-03.pa31 # - sig: fstarr.64 vs1, vs2
Darrays-06.pa30 # - sig: starr vs1, vs2
/arkcompiler/runtime_core/static_core/isa/
Disa.yaml1621 acc = (vs1 + vs2) % 2^32
1623 acc = (vs1 - vs2) % 2^32
1625 acc = (vs1 * vs2) % 2^32
1627 acc = vs1 & vs2
1629 acc = vs1 | vs2
1631 acc = vs1 ^ vs2
1633 acc = (vs1 << (vs2 & 0x1f)) % 2^32
1635 acc = vs1 >> (vs2 & 0x1f)
1637 acc = (vs1 < 0) ? ~(~vs1 >> vs2 & 0x1f) : vs1 >> vs2 & 0x1f
1757 if vs1 == INT32_MIN and vs2 == -1 then
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/arkcompiler/runtime_core/static_core/verification/absint/
Dabs_int_inl.h1785 uint16_t vs1 = inst_.GetVReg<FORMAT, 0x00>(); in HandleInitobj() local
1790 std::array<int, 4UL> regs {vs1, vs2, vs3, vs4}; in HandleInitobj()
1799 uint16_t vs1 = inst_.GetVReg<FORMAT, 0x00>(); in HandleInitobjShort() local
1802 std::array<int, 2UL> regs {vs1, vs2}; in HandleInitobjShort()
2574 uint16_t vs1 = inst_.GetVReg<FORMAT, 0x00>(); in HandleEtsLaunchShort() local
2588 std::array<int, 2UL> regs {vs1, vs2}; in HandleEtsLaunchShort()
2597 uint16_t vs1 = inst_.GetVReg<FORMAT, 0x00>(); in HandleEtsLaunch() local
2613 std::array<int, 4UL> regs {vs1, vs2, vs3, vs4}; in HandleEtsLaunch()
2647 uint16_t vs1 = inst_.GetVReg<FORMAT, 0x00>(); in HandleEtsLaunchVirtShort() local
2660 std::array<int, 2UL> regs {vs1, vs2}; in HandleEtsLaunchVirtShort()
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/arkcompiler/runtime_core/static_core/irtoc/scripts/
Dinterpreter.irt946 macro(:"handle_#{op.downcase}_v4_v4") do |vs1, vs2|
947 set_acc_primitive(send(op, vs1, vs2).i32).i32
1011 macro(:"handle_#{op.downcase}_v4_v4") do |vs1, vs2|
1016 set_acc_primitive(send(op, vs1, vs2).i32)
1202 macro(:"handle_starr_#{size}_v4_v4") do |vs1, vs2|
1203 If(vs1, 0).EQ.Unlikely {
1207 len_array := LoadI(vs1).Imm(Constants::ARRAY_LENGTH_OFFSET).i32
1213 Store(vs1, elem_offset, acc.i32).send(:"i#{size}")
1218 macro(:"handle_#{name}_v4_v4") do |vs1, vs2|
1219 If(vs1, 0).EQ.Unlikely {
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/arkcompiler/runtime_core/static_core/runtime/interpreter/
Dinterpreter-inl.h2977 uint16_t vs1 = this->GetInst().template GetVReg<FORMAT, 0>(); in HandleArrayStore() local
2981 << "store v" << vs1 << ", v" << vs2; in HandleArrayStore()
2983 … auto *array = static_cast<coretypes::Array *>(this->GetFrame()->GetVReg(vs1).GetReference()); in HandleArrayStore()
3581 uint16_t vs1 = this->GetInst().template GetVReg<FORMAT>(); in HandleBinaryOp2() local
3584 << "binop2 v" << vs1; in HandleBinaryOp2()
3586 OpT v2 = this->GetFrame()->GetVReg(vs1).template GetAs<OpT>(); in HandleBinaryOp2()
3626 uint16_t vs1 = this->GetInst().template GetVReg<FORMAT, 0>(); in HandleBinaryOp() local
3630 << "binop2 v" << vs1 << ", v" << vs2; in HandleBinaryOp()
3632 OpT v1 = this->GetFrame()->GetVReg(vs1).template GetAs<OpT>(); in HandleBinaryOp()
3647 uint16_t vs1 = this->GetInst().template GetVReg<FORMAT, 0>(); in HandleBinaryOpV() local
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