| /kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/ |
| D | regs-uart.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
13 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
15 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
16 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
17 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
20 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
21 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
22 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
23 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
|
| D | st,stm32-fmc2-ebi-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/hamradio/ |
| D | z8530.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Write Register 0 */
37 /* Write Register 1 */
39 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
50 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
52 /* Write Register #2 (Interrupt Vector) */
54 /* Write Register 3 */
56 #define RxENABLE 0x1 /* Rx Enable */
59 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/hamradio/ |
| D | z8530.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Write Register 0 */
37 /* Write Register 1 */
39 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
40 #define TxINT_ENAB 0x2 /* Tx Int Enable */
50 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
52 /* Write Register #2 (Interrupt Vector) */
54 /* Write Register 3 */
56 #define RxENABLE 0x1 /* Rx Enable */
59 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-sa1100/include/mach/ |
| D | SA-1100.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
81 * Controller (UDC) Control Register (read/write).
83 * Controller (UDC) Address Register (read/write).
86 * (read/write).
89 * (read/write).
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/mach-sa1100/include/mach/ |
| D | SA-1100.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
81 * Controller (UDC) Control Register (read/write).
83 * Controller (UDC) Address Register (read/write).
86 * (read/write).
89 * (read/write).
[all …]
|
| /kernel/linux/linux-6.6/Documentation/ABI/testing/ |
| D | sysfs-driver-xdata | 1 What: /sys/class/misc/drivers/dw-xdata-pcie.<device>/write
5 Description: Allows the user to enable the PCIe traffic generator which
6 will create write TLPs frames - from the Root Complex to the
10 Write y/1/on to enable, n/0/off to disable
13 echo 1 > /sys/class/misc/dw-xdata-pcie.<device>/write
15 echo 0 > /sys/class/misc/dw-xdata-pcie.<device>/write
21 cat /sys/class/misc/dw-xdata-pcie.<device>/write
24 The file is read and write.
26 What: /sys/class/misc/dw-xdata-pcie.<device>/read
30 Description: Allows the user to enable the PCIe traffic generator which
[all …]
|
| /kernel/linux/linux-6.6/drivers/tty/serial/ |
| D | sunzilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
30 /* Write Register 0 */
61 /* Write Register 1 */
63 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
75 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
77 /* Write Register #2 (Interrupt Vector) */
79 /* Write Register 3 */
81 #define RxENAB 0x1 /* Rx Enable */
[all …]
|
| D | zs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
34 u8 regs[ZS_NUM_REGS]; /* Channel write registers. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
59 /* Write Register 0 (Command) */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
91 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
103 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
105 /* Write Register 2 (Interrupt Vector) */
[all …]
|
| D | ip22zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
38 /* Write Register 0 */
69 /* Write Register 1 */
71 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
83 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
85 /* Write Register #2 (Interrupt Vector) */
87 /* Write Register 3 */
89 #define RxENAB 0x1 /* Rx Enable */
[all …]
|
| D | pmac_zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
[all …]
|
| /kernel/linux/linux-5.10/drivers/tty/serial/ |
| D | sunzilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
30 /* Write Register 0 */
61 /* Write Register 1 */
63 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
64 #define TxINT_ENAB 0x2 /* Tx Int Enable */
75 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
77 /* Write Register #2 (Interrupt Vector) */
79 /* Write Register 3 */
81 #define RxENAB 0x1 /* Rx Enable */
[all …]
|
| D | zs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
34 u8 regs[ZS_NUM_REGS]; /* Channel write registers. */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
59 /* Write Register 0 (Command) */
90 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
91 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
92 #define TxINT_ENAB 0x2 /* Tx Int Enable */
103 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
105 /* Write Register 2 (Interrupt Vector) */
[all …]
|
| D | ip22zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
38 /* Write Register 0 */
69 /* Write Register 1 */
71 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
83 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
85 /* Write Register #2 (Interrupt Vector) */
87 /* Write Register 3 */
89 #define RxENAB 0x1 /* Rx Enable */
[all …]
|
| D | pmac_zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
74 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
76 return uap->mate; in pmz_get_port_A()
88 writeb(reg, port->control_reg); in read_zsreg()
89 return readb(port->control_reg); in read_zsreg()
95 writeb(reg, port->control_reg); in write_zsreg()
96 writeb(value, port->control_reg); in write_zsreg()
101 return readb(port->data_reg); in read_zsdata()
106 writeb(data, port->data_reg); in write_zsdata()
[all …]
|
| /kernel/linux/linux-6.6/drivers/infiniband/ulp/rtrs/ |
| D | rtrs-clt-stats.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2014 - 2018 ProfitBricks GmbH. All rights reserved.
6 * Copyright (c) 2018 - 2019 1&1 IONOS Cloud GmbH. All rights reserved.
7 * Copyright (c) 2019 - 2020 1&1 IONOS SE. All rights reserved.
12 #include "rtrs-clt.h"
16 struct rtrs_clt_path *clt_path = to_clt_path(con->c.path); in rtrs_clt_update_wc_stats()
17 struct rtrs_clt_stats *stats = clt_path->stats; in rtrs_clt_update_wc_stats()
22 s = get_cpu_ptr(stats->pcpu_stats); in rtrs_clt_update_wc_stats()
23 if (con->cpu != cpu) { in rtrs_clt_update_wc_stats()
24 s->cpu_migr.to++; in rtrs_clt_update_wc_stats()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/cache/ |
| D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
[all …]
|
| /kernel/linux/linux-5.10/include/linux/ |
| D | fsl_ifc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * - IFC version 1.0 implements 4 banks.
22 * - IFC version 1.1 onward implements 8 banks.
35 * CSPR - Chip Select Property Register
47 /* Write Protect */
69 (__ilog2(n) - IFC_AMASK_SHIFT))
74 /* Enable ECC Encoder */
81 /* Enable ECC Decoder */
110 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
111 /* Time for Read Enable High to Output High Impedance */
[all …]
|
| /kernel/linux/linux-6.6/include/linux/ |
| D | fsl_ifc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * - IFC version 1.0 implements 4 banks.
22 * - IFC version 1.1 onward implements 8 banks.
35 * CSPR - Chip Select Property Register
47 /* Write Protect */
69 (__ilog2(n) - IFC_AMASK_SHIFT))
74 /* Enable ECC Encoder */
81 /* Enable ECC Decoder */
110 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
111 /* Time for Read Enable High to Output High Impedance */
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-pcie-idio-24.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES PCIe-IDIO-24 family
15 * This driver supports the following ACCES devices: PCIe-IDIO-24,
16 * PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12.
35 * 0: Enable Interrupt Sources (Bit 0)
36 * 1: Enable Interrupt Sources (Bit 1)
38 * 3: Mailbox Interrupt Enable
39 * 4: Power Management Interrupt Enable
41 * 6: Slave Read Local Data Parity Check Error Enable
43 * 8: Internal PCI Wire Interrupt Enable
[all …]
|
| /kernel/linux/linux-5.10/drivers/infiniband/ulp/rtrs/ |
| D | rtrs-clt-stats.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2014 - 2018 ProfitBricks GmbH. All rights reserved.
6 * Copyright (c) 2018 - 2019 1&1 IONOS Cloud GmbH. All rights reserved.
7 * Copyright (c) 2019 - 2020 1&1 IONOS SE. All rights reserved.
12 #include "rtrs-clt.h"
16 struct rtrs_clt_sess *sess = to_clt_sess(con->c.sess); in rtrs_clt_update_wc_stats()
17 struct rtrs_clt_stats *stats = sess->stats; in rtrs_clt_update_wc_stats()
22 s = this_cpu_ptr(stats->pcpu_stats); in rtrs_clt_update_wc_stats()
23 if (unlikely(con->cpu != cpu)) { in rtrs_clt_update_wc_stats()
24 s->cpu_migr.to++; in rtrs_clt_update_wc_stats()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-pxa/ |
| D | regs-u2d.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define U2DCR_SPEOREN (1 << 27) /* Short Packet EOR INTR generation Enable */
21 #define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */
28 #define U2DCR_UDE (1 << 0) /* U2D Enable */
32 #define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */
33 #define U2DINT_SOF (1 << 30) /* Interrupt - SOF */
34 #define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */
35 #define U2DINT_RU (1 << 28) /* Interrupt - Resume */
36 #define U2DINT_SU (1 << 27) /* Interrupt - Suspend */
37 #define U2DINT_RS (1 << 26) /* Interrupt - Reset */
[all …]
|