1 /* ---------------------------------------------------------------------------- 2 * Copyright (c) Huawei Technologies Co., Ltd. 2022-2023. All rights reserved. 3 * Description : Cache operations HeadFile 4 * Author: Huawei LiteOS Team 5 * Create : 2022-12-20 6 * Redistribution and use in source and binary forms, with or without modification, 7 * are permitted provided that the following conditions are met: 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 11 * of conditions and the following disclaimer in the documentation and/or other materials 12 * provided with the distribution. 13 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 14 * to endorse or promote products derived from this software without specific prior written 15 * permission. 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * ---------------------------------------------------------------------------- */ 28 29 /** 30 * @defgroup cache 31 * @ingroup kernel 32 */ 33 34 #ifndef _ARCH_CACHE_H 35 #define _ARCH_CACHE_H 36 37 #include "los_typedef.h" 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 typedef enum { 44 CACHE_4KB = 0, 45 CACHE_8KB = 2, 46 CACHE_16KB = 4, 47 CACHE_32KB = 6, 48 CACHE_64KB = 8, 49 } CacheSize; 50 51 typedef enum { 52 CACHE_PREF_1_LINES = 0, 53 CACHE_PREF_2_LINES = 1, 54 CACHE_PREF_3_LINES = 2, 55 CACHE_PREF_4_LINES = 3, 56 CACHE_PREF_5_LINES = 4, 57 CACHE_PREF_6_LINES = 5, 58 CACHE_PREF_7_LINES = 6, 59 CACHE_PREF_8_LINES = 7, 60 CACHE_PREF_LINES_MAX, 61 } CachePrefLines; 62 63 /* riscv cache register config */ 64 /* 65 * csr_bit[0] ICEN Instruction cache is enabled when this bit is set to 1b1. Default is disabled. 66 * Bit[2:1] ICS Instruction cache size: 2b00=4KB, 2b01=8KB, 2b10=16KB, 2b11=32KB. Default is 32KB 67 */ 68 #define ICCTL 0x7C0 69 #define ICCTL_ENABLE 0x1 70 71 /* 72 * Bit[0] DCEN Data cache is enabled when this bit is set to 1b1. Default is disabled. 73 * Bit[2:1] DCS Data cache size: 2b00=4KB, 2b01=8KB, 2b10=16KB, 2b11=32KB. Default is 32KB 74 */ 75 #define DCCTL 0x7C1 76 #define DCCTL_ENABLE 0x1 77 78 /* 79 * Bit[0] VA Instruction cache invalidation by all or VA: 1b0=all, 1b1=VA. 80 * Bit[2] ICIV Initiate instruction cache invalidation when this bit is set to 1b1. 81 When the instruction cache invalidation is by VA, the virtual address is specified in icinva CSR 82 */ 83 #define ICMAINT 0x7C2 84 #define DCMAINT 0x7C3 85 #define ICINCVA 0x7C4 86 #define DCINCVA 0x7C5 87 88 #define VA 0x1 89 #define ICIV (0x1U << 2) 90 #define DCIV (0x1U << 2) 91 #define DCC (0x1U << 3) 92 93 #define ICACHE_BY_ALL ICIV 94 #define ICACHE_BY_VA (ICIV | VA) 95 96 #define DCACHE_INV_BY_VA (DCIV | VA) 97 #define DCACHE_INV_BY_ALL DCIV 98 #define DCACHE_CLEAN_ALL DCC 99 #define DCACHE_CLEAN_BY_VA (DCC | VA) 100 #define DCACHE_FLUSH_BY_VA (DCC | DCIV | VA) 101 #define DCACHE_FLUSH_ALL (DCC | DCIV) 102 103 #define APREFI 0x7C6 104 #define APREFD 0x7C7 105 #define IAPEN 0x1 106 #define SAPEN (0x1U << 4) 107 108 #define CACHE_LINE_SIZE 32U 109 110 /** 111 * @ingroup cache 112 * @brief enable ICache. 113 * 114 * @par Description: 115 * This API is used to enable ICache. 116 * @attention 117 * <ul> 118 * <li>The API is just enable ICache.</li> 119 * <li>.</li> 120 * </ul> 121 * @param icclSize [IN] The Instruction cache size. 122 * @retval UINT32 return LOS_OK, or return failed. 123 * @par Dependency: 124 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 125 * @since Huawei LiteOS V200R002C00 126 */ 127 UINT32 ArchICacheEnable(CacheSize icclSize); 128 129 /** 130 * @ingroup cache 131 * @brief enable DCache. 132 * 133 * @par Description: 134 * This API is used to enable DCache. 135 * @attention 136 * <ul> 137 * <li>The API is just enable DCache.</li> 138 * <li>.</li> 139 * </ul> 140 * @param dcclSize [IN] The Data cache size. 141 * @retval UINT32 return LOS_OK, or return failed. 142 * @par Dependency: 143 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 144 * @since Huawei LiteOS V200R002C00 145 */ 146 UINT32 ArchDCacheEnable(CacheSize dcclSize); 147 148 /** 149 * @ingroup cache 150 * @brief Init instruction cache auto prefetch. 151 * 152 * @par Description: 153 * This API is used to Init instruction cache auto prefetch ICL value as 1-8. 154 * @attention 155 * <ul> 156 * <li>The API is just to Init instruction cache auto prefetch ICL value as 1-8.</li> 157 * <li>.</li> 158 * </ul> 159 * @param iclValue [IN] The Instruction cache auto prefetch value. 160 * @retval UINT32 return LOS_OK, or return failed. 161 * @par Dependency: 162 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 163 * @since Huawei LiteOS V200R002C00 164 */ 165 UINT32 ArchICachePrefetchEnable(CachePrefLines iclValue); 166 167 /** 168 * @ingroup cache 169 * @brief Init data cache auto prefetch. 170 * 171 * @par Description: 172 * This API is used to Init data cache auto prefetch ICL and SCL value as 1-8. 173 * @attention 174 * <ul> 175 * <li>The API is just to Init data cache auto prefetch ICL and SCL value as 1-8.</li> 176 * <li>.</li> 177 * </ul> 178 * @param iclValue [IN] The Data cache auto prefetch value. 179 * @param sclValue [IN] The Data cache auto prefetch value. 180 * @retval UINT32 return LOS_OK, or return failed. 181 * @par Dependency: 182 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 183 * @since Huawei LiteOS V200R002C00 184 */ 185 UINT32 ArchDCachePrefetchEnable(CachePrefLines iclValue, CachePrefLines sclValue); 186 187 /** 188 * @ingroup cache 189 * @brief flush DCache. 190 * 191 * @par Description: 192 * This API is used to flush DCache by Va. 193 * @attention 194 * <ul> 195 * <li>The base address will be aligned to CACHE_LINE_SIZE if it's not aligned to CACHE_LINE_SIZE.</li> 196 * <li>.</li> 197 * </ul> 198 * @param baseAddr [IN] The start address need flush. 199 * @param size [IN] The size of flush memory. 200 * @par Dependency: 201 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 202 * @since Huawei LiteOS V200R002C00 203 */ 204 VOID ArchDCacheFlushByVa(UINTPTR baseAddr, UINT32 size); 205 206 /** 207 * @ingroup cache 208 * @brief flush ICache. 209 * 210 * @par Description: 211 * This API is used to flush ICache by Va. 212 * @attention 213 * <ul> 214 * <li>The base address will be aligned to CACHE_LINE_SIZE if it's not aligned to CACHE_LINE_SIZE.</li> 215 * <li>.</li> 216 * </ul> 217 * @param baseAddr [IN] The start address need flush. 218 * @param size [IN] The size of flush memory. 219 * @par Dependency: 220 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 221 * @since Huawei LiteOS V200R002C00 222 */ 223 VOID ArchICacheFlushByVa(UINTPTR baseAddr, UINT32 size); 224 225 /** 226 * @ingroup cache 227 * @brief invalid DCache. 228 * 229 * @par Description: 230 * This API is used to invalid DCache by Va. 231 * @attention 232 * <ul> 233 * <li>The base address will be aligned to CACHE_LINE_SIZE if it's not aligned to CACHE_LINE_SIZE.</li> 234 * <li>.</li> 235 * </ul> 236 * @param baseAddr [IN] The start address need flush. 237 * @param size [IN] The size of flush memory. 238 * @par Dependency: 239 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 240 * @since Huawei LiteOS V200R002C00 241 */ 242 VOID ArchDCacheInvByVa(UINTPTR baseAddr, UINT32 size); 243 244 /** 245 * @ingroup cache 246 * @brief clean DCache. 247 * 248 * @par Description: 249 * This API is used to clean DCache. 250 * @attention 251 * <ul> 252 * <li>The API will clean DCache according to based address and input size.</li> 253 * <li>.</li> 254 * </ul> 255 * @par Dependency: 256 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 257 * @since Huawei LiteOS V200R002C00 258 */ 259 VOID ArchDCacheCleanByVa(UINTPTR baseAddr, UINT32 size); 260 261 /** 262 * @ingroup cache 263 * @brief flush ICache by start address and end address. 264 * 265 * @par Description: 266 * This API is used to flush DCache by Va. 267 * @attention 268 * <ul> 269 * <li>The startAddr or endAddr address will be aligned to CACHE_LINE_SIZE if it's not aligned to CACHE_LINE_SIZE.</li> 270 * <li>.</li> 271 * </ul> 272 * @param startAddr [IN] The start address need flush. 273 * @param endAddr [IN] The end address need flush. 274 * @par Dependency: 275 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 276 * @since Huawei LiteOS V200R003C00 277 */ 278 VOID ArchICacheFlushByAddr(UINTPTR startAddr, UINTPTR endAddr); 279 280 /** 281 * @ingroup cache 282 * @brief flush DCache by start address and end address. 283 * 284 * @par Description: 285 * This API is used to flush DCache by Va. 286 * @attention 287 * <ul> 288 * <li>The startAddr or endAddr address will be aligned to CACHE_LINE_SIZE if it's not aligned to CACHE_LINE_SIZE.</li> 289 * <li>.</li> 290 * </ul> 291 * @param startAddr [IN] The start address need flush. 292 * @param endAddr [IN] The end address need flush. 293 * @par Dependency: 294 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 295 * @since Huawei LiteOS V200R003C00 296 */ 297 VOID ArchDCacheFlushByAddr(UINTPTR startAddr, UINTPTR endAddr); 298 299 /** 300 * @ingroup cache 301 * @brief clean DCache by start address and end address. 302 * 303 * @par Description: 304 * This API is used to clean DCache by Va. 305 * @attention 306 * <ul> 307 * <li>The startAddr or endAddr address will be aligned to CACHE_LINE_SIZE if it's not aligned to CACHE_LINE_SIZE.</li> 308 * <li>.</li> 309 * </ul> 310 * @param startAddr [IN] The start address need clean. 311 * @param endAddr [IN] The end address need clean. 312 * @par Dependency: 313 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 314 * @since Huawei LiteOS V200R003C00 315 */ 316 VOID ArchDCacheCleanByAddr(UINTPTR startAddr, UINTPTR endAddr); 317 318 /** 319 * @ingroup cache 320 * @brief invalidate DCache by start address and end address. 321 * 322 * @par Description: 323 * This API is used to flush DCache by Va. 324 * @attention 325 * <ul> 326 * <li>The startAddr or endAddr address will be aligned to CACHE_LINE_SIZE if it's not aligned to CACHE_LINE_SIZE.</li> 327 * <li>.</li> 328 * </ul> 329 * @param startAddr [IN] The start address need invalidate. 330 * @param endAddr [IN] The end address need invalidate. 331 * @par Dependency: 332 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 333 * @since Huawei LiteOS V200R003C00 334 */ 335 VOID ArchDCacheInvByAddr(UINTPTR startAddr, UINTPTR endAddr); 336 337 /** 338 * @ingroup cache 339 * @brief flush ICache. 340 * 341 * @par Description: 342 * This API is used to flush ICache. 343 * @attention 344 * <ul> 345 * <li>The API will flush all ICache.</li> 346 * <li>.</li> 347 * </ul> 348 * @par Dependency: 349 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 350 * @since Huawei LiteOS V200R002C00 351 */ 352 VOID ArchICacheFlush(VOID); 353 354 /** 355 * @ingroup cache 356 * @brief flush DCache. 357 * 358 * @par Description: 359 * This API is used to flush DCache. 360 * @attention 361 * <ul> 362 * <li>The API will flush all DCache, the size is 32K.</li> 363 * <li>.</li> 364 * </ul> 365 * @par Dependency: 366 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 367 * @since Huawei LiteOS V200R002C00 368 */ 369 VOID ArchDCacheFlush(VOID); 370 371 /** 372 * @ingroup cache 373 * @brief Invalidate DCache. 374 * 375 * @par Description: 376 * This API is used to Invalidate DCache. 377 * @attention 378 * <ul> 379 * <li>The API will Invalidate all DCache.</li> 380 * <li>.</li> 381 * </ul> 382 * @par Dependency: 383 * <ul><li>cache.h: the header file that contains the API declaration.</li></ul> 384 * @since Huawei LiteOS V200R002C00 385 */ 386 VOID ArchDCacheInvalidate(VOID); 387 388 #define flush_dcache(start, end) ArchDCacheFlushByAddr(start, end) 389 #define flush_icache() ArchICacheFlush() 390 391 #ifdef __cplusplus 392 } 393 #endif /* __cplusplus */ 394 395 #endif /* _ARCH_CACHE_H */ 396