1 /* ----------------------------------------------------------------------------
2 * Copyright (c) Huawei Technologies Co., Ltd. 2022-2023. All rights reserved.
3 * Description: CPU Operations HeadFile
4 * Author: Huawei LiteOS Team
5 * Create: 2022-12-20
6 * Redistribution and use in source and binary forms, with or without modification,
7 * are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
11 * of conditions and the following disclaimer in the documentation and/or other materials
12 * provided with the distribution.
13 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
14 * to endorse or promote products derived from this software without specific prior written
15 * permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * --------------------------------------------------------------------------- */
28
29 #ifndef _ARCH_CPU_H
30 #define _ARCH_CPU_H
31
32 #ifndef __ASSEMBLER__
33 #include "los_typedef.h"
34 #endif
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif /* __cplusplus */
39
40 #ifdef __riscv64
41 #define LREG ld
42 #define SREG sd
43 #define FLREG fld
44 #define FSREG fsd
45 #define REGBYTES 8
46 #define FPUREGBYTES 8
47 #else
48 #define LREG lw
49 #define SREG sw
50 #define REGBYTES 4
51 #ifdef LOSCFG_ARCH_FPU_DOUBLE
52 #define FLREG fld
53 #define FSREG fsd
54 #define FPUREGBYTES 8
55 #else
56 #define FLREG flw
57 #define FSREG fsw
58 #define FPUREGBYTES 4
59 #endif
60 #endif
61
62 /* |-----------------------------| if define LOSCFG_ARCH_FPU_ENABLE
63 | FPU_STATUS_REG_NUM | fcsr, res[3]
64 |-----------------------------|
65 | FPU_CALLER_REG_NUM | ft0 - ft11, fa0 - fa7
66 |-----------------------------|
67 | FPU_CALLEE_REG_NUM | fs0 - fs11
68 |-----------------------------| endif LOSCFG_ARCH_FPU_ENABLE
69 | INTEGER_CALLER_REG_NUM | t0 - t6, a0 - a7, ra
70 |-----------------------------|
71 | INTEGER_CALLEE_REG_NUM | s0 - s11
72 |-----------------------------| if in Exc context
73 | EXC_SPECIAL_REG_NUM | ccause,mcause,mtval,gp
74 |-----------------------------| endif in Exc context
75 */
76 #define TP_STACK_INDEX 2
77 #define SP_STACK_INDEX 3
78
79 #define EXC_SPECIAL_REG_NUM 4 // ccause,mcause,mtval,gp
80 #define EXC_SPECIAL_REG_SIZE (4 * REGBYTES)
81
82 #define INTEGER_CALLER_REG_NUM 16
83 #define INTEGER_CALLEE_REG_NUM 12
84 #define CPU_SPECIAL_REG_NUM 4 // mstatus,mepc,tp,sp
85 #define INTEGER_REG_NUM (INTEGER_CALLER_REG_NUM + INTEGER_CALLEE_REG_NUM + CPU_SPECIAL_REG_NUM)
86
87 #define INTEGER_CALLER_REG_SIZE (INTEGER_CALLER_REG_NUM * REGBYTES)
88 #define INTEGER_CALLEE_REG_SIZE (INTEGER_CALLEE_REG_NUM * REGBYTES)
89 #define CPU_SPECIAL_REG_SIZE (CPU_SPECIAL_REG_NUM * REGBYTES)
90 #define INTEGER_REG_SIZE (INTEGER_CALLER_REG_SIZE + INTEGER_CALLEE_REG_SIZE + CPU_SPECIAL_REG_SIZE)
91
92 #ifdef LOSCFG_ARCH_FPU_ENABLE
93 #define FPU_STATUS_REG_NUM 4 // fcsr,res[3]
94 #define FPU_CALLER_REG_NUM 20
95 #define FPU_CALLEE_REG_NUM 12
96 #define FPU_EXTENSION_REG_NUM (FPU_CALLER_REG_NUM + FPU_CALLEE_REG_NUM)
97 #define FPU_STATUS_REG_SIZE (FPU_STATUS_REG_NUM * REGBYTES)
98 #define FPU_CALLER_REG_SIZE (FPU_CALLER_REG_NUM * FPUREGBYTES)
99 #define FPU_CALLEE_REG_SIZE (FPU_CALLEE_REG_NUM * FPUREGBYTES)
100 #define FPU_EXTENSION_REG_SIZE (FPU_CALLER_REG_SIZE + FPU_CALLEE_REG_SIZE)
101
102 #define FCSR_STACK_OFFSET (INTEGER_REG_SIZE + FPU_EXTENSION_REG_SIZE)
103
104 #define INT_SIZE_ON_STACK (INTEGER_REG_SIZE + FPU_EXTENSION_REG_SIZE + FPU_STATUS_REG_SIZE)
105 #else
106 #define INT_SIZE_ON_STACK INTEGER_REG_SIZE
107 #endif
108
109 /* risc-v mstatus Register */
110 #define LOS_MSTATUS_MIE 0x00000008
111 #define LOS_MSTATUS_MPIE 0x00000080
112 #define LOS_MSTATUS_MPP 0x00001800
113 #define LOS_MSTATUS_FS 0x00006000
114 #ifdef LOSCFG_ARCH_LINX_M
115 #define LOS_MCAUSE_UOP 0x0100F000
116 #endif
117 #ifdef LOSCFG_ARCH_FPU_ENABLE
118 #define LOSCFG_MSTATUS_M (LOS_MSTATUS_MPP | LOS_MSTATUS_MPIE | LOS_MSTATUS_FS)
119 #else
120 #define LOSCFG_MSTATUS_M (LOS_MSTATUS_MPP | LOS_MSTATUS_MPIE)
121 #endif
122 #define UINT32_CUT_MASK 0xFFFFFFFF
123 #define UINT8_CUT_MASK 0xFF
124
125 #ifdef LOSCFG_ARCH_LINX_M
126 #define NUM_HAL_INTERRUPT_NMI 0xFFF
127 #endif
128
129 #ifndef __ASSEMBLER__
ArchCurrCpuid(VOID)130 STATIC INLINE UINT32 ArchCurrCpuid(VOID)
131 {
132 return 0;
133 }
134
ArchSPGet(VOID)135 STATIC INLINE UINT32 ArchSPGet(VOID)
136 {
137 UINT32 val;
138 __asm__ volatile("mv %0, sp" : "=r"(val));
139 return val;
140 }
141
ArchCpuInfo(VOID)142 STATIC INLINE const CHAR *ArchCpuInfo(VOID)
143 {
144 return "unknown";
145 }
146 #endif /* __ASSEMBLER__ */
147
148 #ifdef __cplusplus
149 }
150 #endif /* __cplusplus */
151
152 #endif
153