1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * Description: riscv encoding 15 * 16 * Create: 2021-07-21 17 */ 18 19 #ifndef ARCH_ENCODING_H 20 #define ARCH_ENCODING_H 21 22 #ifdef __cplusplus 23 #if __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 #endif /* __cplusplus */ 27 28 #define MCAUSE 0x342 29 #define MCAUSE_INSN_MISALIGN 0x0 30 #define MCAUSE_INSN_FAULT 0x1 31 #define MCAUSE_INSN_ILLEGAL 0x2 32 #define MCAUSE_BRKT 0x3 33 #define MCSUSE_LOAD_MISALIGN 0x4 34 #define MCAUSE_LOAD_FAULT 0x5 35 #define MCAUSE_AMO_MISALIGN 0x6 36 #define MCAUSE_AMO_FAULT 0x7 37 #define MCAUSE_ECALL_U 0x8 38 #define MCAUSE_ECALL_M 0xB 39 #define MCAUSE_INSN_PAGE_FAULT 0xC 40 #define MCAUSE_LOAD_PAGE_FAULT 0xD 41 #define MCAUSE_AMO_PAGE_FAULT 0xF 42 43 #define EXC_SIZE_ON_STACK (160) // 16byte align 44 45 #define MSTATUS_UIE 0x00000001 46 #define MSTATUS_SIE 0x00000002 47 #define MSTATUS_HIE 0x00000004 48 #define MSTATUS_MIE 0x00000008 49 #define MSTATUS_UPIE 0x00000010 50 #define MSTATUS_SPIE 0x00000020 51 #define MSTATUS_HPIE 0x00000040 52 #define MSTATUS_MPIE 0x00000080 53 #define MSTATUS_SPP 0x00000100 54 #define MSTATUS_HPP 0x00000600 55 #define MSTATUS_MPP 0x00001800 56 #define MSTATUS_FS 0x00006000 57 #define MSTATUS_XS 0x00018000 58 #define MSTATUS_MPRV 0x00020000 59 #define MSTATUS_PUM 0x00040000 60 #define MSTATUS_VM 0x1F000000 61 #define MSTATUS32_SD 0x80000000 62 #define MSTATUS64_SD 0x8000000000000000 63 64 #define MCAUSE32_CAUSE 0x7FFFFFFF 65 #define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF 66 #define MCAUSE32_INT 0x80000000 67 #define MCAUSE64_INT 0x8000000000000000 68 69 #define SSTATUS_UIE 0x00000001 70 #define SSTATUS_SIE 0x00000002 71 #define SSTATUS_UPIE 0x00000010 72 #define SSTATUS_SPIE 0x00000020 73 #define SSTATUS_SPP 0x00000100 74 #define SSTATUS_FS 0x00006000 75 #define SSTATUS_XS 0x00018000 76 #define SSTATUS_PUM 0x00040000 77 #define SSTATUS32_SD 0x80000000 78 #define SSTATUS64_SD 0x8000000000000000 79 80 #define IRQ_S_SOFT 1 81 #define IRQ_H_SOFT 2 82 #define IRQ_M_SOFT 3 83 #define IRQ_S_TIMER 5 84 #define IRQ_H_TIMER 6 85 #define IRQ_M_TIMER 7 86 #define IRQ_S_EXT 9 87 #define IRQ_H_EXT 10 88 #define IRQ_M_EXT 11 89 #define IRQ_COP 12 90 #define IRQ_HOST 13 91 #define IRQ_LOCIE0 26 92 #define IRQ_LOCIE1 27 93 #define IRQ_LOCIE2 28 94 #define IRQ_LOCIE3 29 95 #define IRQ_LOCIE4 30 96 #define IRQ_LOCIE5 31 97 98 // rv_custom_local_interrupt 6 -31 99 #define IRQ_LOCIE6 0 100 #define IRQ_LOCIE7 1 101 #define IRQ_LOCIE8 2 102 #define IRQ_LOCIE9 3 103 #define IRQ_LOCIE10 4 104 #define IRQ_LOCIE11 5 105 #define IRQ_LOCIE12 6 106 #define IRQ_LOCIE13 7 107 #define IRQ_LOCIE14 8 108 #define IRQ_LOCIE15 9 109 #define IRQ_LOCIE16 10 110 #define IRQ_LOCIE17 11 111 #define IRQ_LOCIE18 12 112 #define IRQ_LOCIE19 13 113 #define IRQ_LOCIE20 14 114 #define IRQ_LOCIE21 15 115 #define IRQ_LOCIE22 16 116 #define IRQ_LOCIE23 17 117 #define IRQ_LOCIE24 18 118 #define IRQ_LOCIE25 19 119 #define IRQ_LOCIE26 20 120 #define IRQ_LOCIE27 21 121 #define IRQ_LOCIE28 22 122 #define IRQ_LOCIE29 23 123 #define IRQ_LOCIE30 24 124 #define IRQ_LOCIE31 25 125 126 // rv_nmi 127 #define IRQ_NMI 12 128 #define MIP_NMI (1 << IRQ_NMI) 129 130 #define MIP_SSIE (1 << IRQ_S_SOFT) 131 #define MIP_HSIE (1 << IRQ_H_SOFT) 132 #define MIP_MSIE (1 << IRQ_M_SOFT) 133 #define MIP_STIE (1 << IRQ_S_TIMER) 134 #define MIP_HTIE (1 << IRQ_H_TIMER) 135 #define MIP_MTIE (1 << IRQ_M_TIMER) 136 #define MIP_SEIE (1 << IRQ_S_EXT) 137 #define MIP_HEIE (1 << IRQ_H_EXT) 138 #define MIP_MEIE (1 << IRQ_M_EXT) 139 #define MIP_NMIE (1 << IRQ_COP) 140 #define MIP_LOCIE0 (1 << IRQ_LOCIE0) 141 #define MIP_LOCIE1 (1 << IRQ_LOCIE1) 142 #define MIP_LOCIE2 (1 << IRQ_LOCIE2) 143 #define MIP_LOCIE3 (1 << IRQ_LOCIE3) 144 #define MIP_LOCIE4 (1 << IRQ_LOCIE4) 145 #define MIP_LOCIE5 ((uint32_t)1 << IRQ_LOCIE5) 146 147 // rv_custom_csr 148 #define LOCIPD0_LOCIE6 (1 << IRQ_LOCIE6) 149 #define LOCIPD0_LOCIE7 (1 << IRQ_LOCIE7) 150 #define LOCIPD0_LOCIE8 (1 << IRQ_LOCIE8) 151 #define LOCIPD0_LOCIE9 (1 << IRQ_LOCIE9) 152 #define LOCIPD0_LOCIE10 (1 << IRQ_LOCIE10) 153 #define LOCIPD0_LOCIE11 (1 << IRQ_LOCIE11) 154 #define LOCIPD0_LOCIE12 (1 << IRQ_LOCIE12) 155 #define LOCIPD0_LOCIE13 (1 << IRQ_LOCIE13) 156 #define LOCIPD0_LOCIE14 (1 << IRQ_LOCIE14) 157 #define LOCIPD0_LOCIE15 (1 << IRQ_LOCIE15) 158 #define LOCIPD0_LOCIE16 (1 << IRQ_LOCIE16) 159 #define LOCIPD0_LOCIE17 (1 << IRQ_LOCIE17) 160 #define LOCIPD0_LOCIE18 (1 << IRQ_LOCIE18) 161 #define LOCIPD0_LOCIE19 (1 << IRQ_LOCIE19) 162 #define LOCIPD0_LOCIE20 (1 << IRQ_LOCIE20) 163 #define LOCIPD0_LOCIE21 (1 << IRQ_LOCIE21) 164 #define LOCIPD0_LOCIE22 (1 << IRQ_LOCIE22) 165 #define LOCIPD0_LOCIE23 (1 << IRQ_LOCIE23) 166 #define LOCIPD0_LOCIE24 (1 << IRQ_LOCIE24) 167 #define LOCIPD0_LOCIE25 (1 << IRQ_LOCIE25) 168 #define LOCIPD0_LOCIE26 (1 << IRQ_LOCIE26) 169 #define LOCIPD0_LOCIE27 (1 << IRQ_LOCIE27) 170 #define LOCIPD0_LOCIE28 (1 << IRQ_LOCIE28) 171 #define LOCIPD0_LOCIE29 (1 << IRQ_LOCIE29) 172 #define LOCIPD0_LOCIE30 (1 << IRQ_LOCIE30) 173 #define LOCIPD0_LOCIE31 (1 << IRQ_LOCIE31) 174 175 #define PMPCFG0 0 176 #define PMPCFG1 1 177 #define PMPCFG2 2 178 #define PMPCFG3 3 179 180 #define PMPADDR0 0 181 #define PMPADDR1 1 182 #define PMPADDR2 2 183 #define PMPADDR3 3 184 #define PMPADDR4 4 185 #define PMPADDR5 5 186 #define PMPADDR6 6 187 #define PMPADDR7 7 188 #define PMPADDR8 8 189 #define PMPADDR9 9 190 #define PMPADDR10 10 191 #define PMPADDR11 11 192 #define PMPADDR12 12 193 #define PMPADDR13 13 194 #define PMPADDR14 14 195 #define PMPADDR15 15 196 197 // rv_custom_csr 198 #define LOCIPRI0 (0xBC0) 199 #define LOCIPRI1 (0xBC1) 200 #define LOCIPRI2 (0xBC2) 201 #define LOCIPRI3 (0xBC3) 202 203 #define ICCTL (0x7C0) 204 #define DCCTL (0x7C1) 205 #define ICMAINT (0x7C2) 206 #define DCMAINT (0x7C3) 207 #define ICINVA (0x7C4) 208 #define DCINCVA (0x7C5) 209 #define MEMATTRL (0x7D8) 210 #define MEMATTRH (0x7D9) 211 #define LOCIPRI4 (0xBC4) 212 #define LOCIPRI5 (0xBC5) 213 #define LOCIPRI6 (0xBC6) 214 #define LOCIPRI7 (0xBC7) 215 #define LOCIPRI8 (0xBC8) 216 #define LOCIPRI9 (0xBC9) 217 #define LOCIPRI10 (0xBCA) 218 #define LOCIPRI11 (0xBCB) 219 #define LOCIPRI12 (0xBCC) 220 #define LOCIPRI13 (0xBCD) 221 #define LOCIPRI14 (0xBCE) 222 #define LOCIPRI15 (0xBCF) 223 224 #define locipri(x) LOCIPRI##x 225 226 #define EXTERNAL_INTERRUPT_GROUP0 0 227 #define EXTERNAL_INTERRUPT_GROUP1 1 228 #define EXTERNAL_INTERRUPT_GROUP2 2 229 #define EXTERNAL_INTERRUPT_GROUP3 3 230 #define EXTERNAL_INTERRUPT_GROUP4 4 231 #define EXTERNAL_INTERRUPT_GROUP5 5 232 #define EXTERNAL_INTERRUPT_GROUP6 6 233 #define EXTERNAL_INTERRUPT_GROUP7 7 234 235 #define LOCIEN0 0xBE0 236 #define LOCIEN1 0xBE1 237 #define LOCIEN2 0xBE2 238 239 #define LOCIPD0 0xBE8 240 #define LOCIPD1 0xBE9 241 #define LOCIPD2 0xBEA 242 #define LOCIPD3 0xBEB 243 244 /* local interrupt pending clear register */ 245 #define LOCIPCLR 0xBF0 246 #define PRITHD 0xBFE 247 #define CXCPTSC 0xFC2 248 249 #define SIP_SSIP MIP_SSIP 250 #define SIP_STIP MIP_STIP 251 252 #define PRV_U 0 253 #define PRV_S 1 254 #define PRV_H 2 255 #define PRV_M 3 256 257 #define VM_MBARE 0 258 #define VM_MBB 1 259 #define VM_MBBID 2 260 #define VM_SV32 8 261 #define VM_SV39 9 262 #define VM_SV48 10 263 264 #define DEFAULT_RSTVEC 0x00001000 265 #define DEFAULT_NMIVEC 0x00001004 266 #define DEFAULT_MTVEC 0x00001010 267 #define CONFIG_STRING_ADDR 0x0000100C 268 #define EXT_IO_BASE 0x40000000 269 #define DRAM_BASE 0x80000000 270 271 // page table entry (PTE) fields 272 #define PTE_V 0x001 // Valid 273 #define PTE_TYPE 0x01E // Type 274 #define PTE_R 0x020 // Referenced 275 #define PTE_D 0x040 // Dirty 276 #define PTE_SOFT 0x380 // Reserved for Software 277 278 #define PTE_TYPE_TABLE 0x00 279 #define PTE_TYPE_TABLE_GLOBAL 0x02 280 #define PTE_TYPE_URX_SR 0x04 281 #define PTE_TYPE_URWX_SRW 0x06 282 #define PTE_TYPE_UR_SR 0x08 283 #define PTE_TYPE_URW_SRW 0x0A 284 #define PTE_TYPE_URX_SRX 0x0C 285 #define PTE_TYPE_URWX_SRWX 0x0E 286 #define PTE_TYPE_SR 0x10 287 #define PTE_TYPE_SRW 0x12 288 #define PTE_TYPE_SRX 0x14 289 #define PTE_TYPE_SRWX 0x16 290 #define PTE_TYPE_SR_GLOBAL 0x18 291 #define PTE_TYPE_SRW_GLOBAL 0x1A 292 #define PTE_TYPE_SRX_GLOBAL 0x1C 293 #define PTE_TYPE_SRWX_GLOBAL 0x1E 294 295 #define PTE_PPN_SHIFT 10 296 297 #define pte_table(pte) ((0x0000000AU >> ((pte) & 0x1F)) & 1) 298 #define pte_ur(pte) ((0x0000AAA0U >> ((pte) & 0x1F)) & 1) 299 #define pte_uw(pte) ((0x00008880U >> ((pte) & 0x1F)) & 1) 300 #define pte_ux(pte) ((0x0000A0A0U >> ((pte) & 0x1F)) & 1) 301 #define pte_sr(pte) ((0xAAAAAAA0U >> ((pte) & 0x1F)) & 1) 302 #define pte_sw(pte) ((0x88888880U >> ((pte) & 0x1F)) & 1) 303 #define pte_sx(pte) ((0xA0A0A000U >> ((pte) & 0x1F)) & 1) 304 305 #define pte_check_perm(pte, supervisor, store, fetch) \ 306 ((store) ? ((supervisor) ? pte_sw(pte) : pte_uw(pte)) : \ 307 (fetch) ? ((supervisor) ? pte_sx(pte) : pte_ux(pte)) : \ 308 ((supervisor) ? pte_sr(pte) : pte_ur(pte))) 309 310 #ifdef __riscv 311 312 #ifdef __riscv64 313 # define MSTATUS_SD MSTATUS64_SD 314 # define SSTATUS_SD SSTATUS64_SD 315 # define MCAUSE_INT MCAUSE64_INT 316 # define MCAUSE_CAUSE MCAUSE64_CAUSE 317 # define RISCV_PGLEVEL_BITS 9 318 #else 319 # define MSTATUS_SD MSTATUS32_SD 320 # define SSTATUS_SD SSTATUS32_SD 321 # define RISCV_PGLEVEL_BITS 10 322 # define MCAUSE_INT MCAUSE32_INT 323 # define MCAUSE_CAUSE MCAUSE32_CAUSE 324 #endif 325 326 #define RISCV_PGSHIFT 12 327 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) 328 329 #ifndef __ASSEMBLER__ 330 331 #ifdef __GNUC__ 332 333 #define read_csr(reg) ({ unsigned long __tmp; \ 334 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 335 __tmp; }) 336 337 #define write_csr(reg, val) ({ \ 338 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 339 asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ 340 else \ 341 asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) 342 343 #define swap_csr(reg, val) ({ unsigned long __tmp; \ 344 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 345 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ 346 else \ 347 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ 348 __tmp; }) 349 350 #define set_csr(reg, bit) ({ unsigned long __tmp; \ 351 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 352 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 353 else \ 354 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 355 __tmp; }) 356 357 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ 358 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 359 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 360 else \ 361 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 362 __tmp; }) 363 364 // rv_custom_csr 365 #define read_custom_csr(reg) ({ unsigned long __tmp; \ 366 asm volatile ("csrr %0, %1" : "=r"(__tmp) : "i"(reg)); \ 367 __tmp; }) 368 369 #define write_custom_csr_val(reg_addr, val) ({ \ 370 if (__builtin_constant_p(val)) \ 371 asm volatile("li t0," "%0" : : "i"(val) : "%t0"); \ 372 else \ 373 asm volatile("mv t0," "%0" : : "r"(val) : "%t0"); \ 374 asm volatile("csrw %0, t0" :: "i"(reg_addr) : "%t0"); \ 375 }) 376 377 #define set_custom_csr(reg_addr, bit) ({ \ 378 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 379 asm volatile("li t0," "%0" : : "i"(bit) : "%t0"); \ 380 else \ 381 asm volatile("mv t0," "%0" : : "r"(bit) : "%t0"); \ 382 asm volatile("csrs %0, t0" :: "i"(reg_addr) : "%t0"); \ 383 }) 384 385 #define clear_custom_csr(reg_addr, bit) ({ \ 386 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 387 asm volatile("li t0," "%0" : : "i"(bit) : "%t0"); \ 388 else \ 389 asm volatile("mv t0," "%0" : : "r"(bit) : "%t0"); \ 390 asm volatile("csrc %0, t0" :: "i"(reg_addr) : "%t0"); \ 391 }) 392 393 #define rdtime() read_csr(time) 394 #define rdcycle() read_csr(cycle) 395 #define rdinstret() read_csr(instret) 396 397 #endif 398 399 #endif 400 401 #endif 402 403 #ifdef __cplusplus 404 #if __cplusplus 405 } 406 #endif /* __cplusplus */ 407 #endif /* __cplusplus */ 408 409 #endif 410 411