1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE 23 * 24 ***********************************************************************************************************************/ 25 26 /** 27 ************************************************************************************************************************ 28 * @file gfx11addrlib.h 29 * @brief Contains the Gfx11Lib class definition. 30 ************************************************************************************************************************ 31 */ 32 33 #ifndef __GFX11_ADDR_LIB_H__ 34 #define __GFX11_ADDR_LIB_H__ 35 36 #include "addrlib2.h" 37 #include "coord.h" 38 #include "gfx11SwizzlePattern.h" 39 40 namespace Addr 41 { 42 namespace V2 43 { 44 45 /** 46 ************************************************************************************************************************ 47 * @brief GFX11 specific settings structure. 48 ************************************************************************************************************************ 49 */ 50 struct Gfx11ChipSettings 51 { 52 struct 53 { 54 UINT_32 reserved1 : 32; 55 56 // Misc configuration bits 57 UINT_32 reserved2 : 32; 58 }; 59 }; 60 61 /** 62 ************************************************************************************************************************ 63 * @brief GFX11 data surface type. 64 ************************************************************************************************************************ 65 */ 66 enum Gfx11DataType 67 { 68 Gfx11DataColor, 69 Gfx11DataDepthStencil, 70 }; 71 72 const UINT_32 Gfx11LinearSwModeMask = (1u << ADDR_SW_LINEAR); 73 74 const UINT_32 Gfx11Blk256BSwModeMask = (1u << ADDR_SW_256B_D); 75 76 const UINT_32 Gfx11Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) | 77 (1u << ADDR_SW_4KB_D) | 78 (1u << ADDR_SW_4KB_S_X) | 79 (1u << ADDR_SW_4KB_D_X); 80 81 const UINT_32 Gfx11Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) | 82 (1u << ADDR_SW_64KB_D) | 83 (1u << ADDR_SW_64KB_S_T) | 84 (1u << ADDR_SW_64KB_D_T) | 85 (1u << ADDR_SW_64KB_Z_X) | 86 (1u << ADDR_SW_64KB_S_X) | 87 (1u << ADDR_SW_64KB_D_X) | 88 (1u << ADDR_SW_64KB_R_X); 89 90 const UINT_32 Gfx11Blk256KBSwModeMask = (1u << ADDR_SW_256KB_Z_X) | 91 (1u << ADDR_SW_256KB_S_X) | 92 (1u << ADDR_SW_256KB_D_X) | 93 (1u << ADDR_SW_256KB_R_X); 94 95 const UINT_32 Gfx11ZSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 96 (1u << ADDR_SW_256KB_Z_X); 97 98 const UINT_32 Gfx11StandardSwModeMask = (1u << ADDR_SW_4KB_S) | 99 (1u << ADDR_SW_64KB_S) | 100 (1u << ADDR_SW_64KB_S_T) | 101 (1u << ADDR_SW_4KB_S_X) | 102 (1u << ADDR_SW_64KB_S_X) | 103 (1u << ADDR_SW_256KB_S_X); 104 105 const UINT_32 Gfx11DisplaySwModeMask = (1u << ADDR_SW_256B_D) | 106 (1u << ADDR_SW_4KB_D) | 107 (1u << ADDR_SW_64KB_D) | 108 (1u << ADDR_SW_64KB_D_T) | 109 (1u << ADDR_SW_4KB_D_X) | 110 (1u << ADDR_SW_64KB_D_X) | 111 (1u << ADDR_SW_256KB_D_X); 112 113 const UINT_32 Gfx11RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) | 114 (1u << ADDR_SW_256KB_R_X); 115 116 const UINT_32 Gfx11XSwModeMask = (1u << ADDR_SW_4KB_S_X) | 117 (1u << ADDR_SW_4KB_D_X) | 118 (1u << ADDR_SW_64KB_Z_X) | 119 (1u << ADDR_SW_64KB_S_X) | 120 (1u << ADDR_SW_64KB_D_X) | 121 (1u << ADDR_SW_64KB_R_X) | 122 Gfx11Blk256KBSwModeMask; 123 124 const UINT_32 Gfx11TSwModeMask = (1u << ADDR_SW_64KB_S_T) | 125 (1u << ADDR_SW_64KB_D_T); 126 127 const UINT_32 Gfx11XorSwModeMask = Gfx11XSwModeMask | 128 Gfx11TSwModeMask; 129 130 const UINT_32 Gfx11Rsrc1dSwModeMask = (1u << ADDR_SW_LINEAR) | 131 (1u << ADDR_SW_64KB_R_X) | 132 (1u << ADDR_SW_64KB_Z_X) ; 133 134 const UINT_32 Gfx11Rsrc2dSwModeMask = Gfx11LinearSwModeMask | 135 Gfx11DisplaySwModeMask | 136 Gfx11ZSwModeMask | 137 Gfx11RenderSwModeMask; 138 139 const UINT_32 Gfx11Rsrc3dSwModeMask = Gfx11LinearSwModeMask | 140 Gfx11StandardSwModeMask | 141 Gfx11ZSwModeMask | 142 Gfx11RenderSwModeMask | 143 (1u << ADDR_SW_64KB_D_X) | 144 (1u << ADDR_SW_256KB_D_X); 145 146 const UINT_32 Gfx11Rsrc2dPrtSwModeMask = 147 (Gfx11Blk4KBSwModeMask | Gfx11Blk64KBSwModeMask) & ~Gfx11XSwModeMask & Gfx11Rsrc2dSwModeMask; 148 149 const UINT_32 Gfx11Rsrc3dPrtSwModeMask = 150 (Gfx11Blk4KBSwModeMask | Gfx11Blk64KBSwModeMask) & ~Gfx11XSwModeMask & Gfx11Rsrc3dSwModeMask; 151 152 const UINT_32 Gfx11Rsrc3dThin64KBSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 153 (1u << ADDR_SW_64KB_R_X); 154 155 const UINT_32 Gfx11Rsrc3dThin256KBSwModeMask = (1u << ADDR_SW_256KB_Z_X) | 156 (1u << ADDR_SW_256KB_R_X); 157 158 const UINT_32 Gfx11Rsrc3dThinSwModeMask = Gfx11Rsrc3dThin64KBSwModeMask | Gfx11Rsrc3dThin256KBSwModeMask; 159 160 const UINT_32 Gfx11Rsrc3dThickSwModeMask = Gfx11Rsrc3dSwModeMask & ~(Gfx11Rsrc3dThinSwModeMask | Gfx11LinearSwModeMask); 161 162 const UINT_32 Gfx11Rsrc3dThick4KBSwModeMask = Gfx11Rsrc3dThickSwModeMask & Gfx11Blk4KBSwModeMask; 163 164 const UINT_32 Gfx11Rsrc3dThick64KBSwModeMask = Gfx11Rsrc3dThickSwModeMask & Gfx11Blk64KBSwModeMask; 165 166 const UINT_32 Gfx11Rsrc3dThick256KBSwModeMask = Gfx11Rsrc3dThickSwModeMask & Gfx11Blk256KBSwModeMask; 167 168 const UINT_32 Gfx11MsaaSwModeMask = Gfx11ZSwModeMask | 169 Gfx11RenderSwModeMask; 170 171 const UINT_32 Dcn32SwModeMask = (1u << ADDR_SW_LINEAR) | 172 (1u << ADDR_SW_64KB_D) | 173 (1u << ADDR_SW_64KB_D_T) | 174 (1u << ADDR_SW_64KB_D_X) | 175 (1u << ADDR_SW_64KB_R_X) | 176 (1u << ADDR_SW_256KB_D_X) | 177 (1u << ADDR_SW_256KB_R_X); 178 179 const UINT_32 Size256K = 262144u; 180 const UINT_32 Log2Size256K = 18u; 181 182 /** 183 ************************************************************************************************************************ 184 * @brief This class is the GFX11 specific address library 185 * function set. 186 ************************************************************************************************************************ 187 */ 188 class Gfx11Lib : public Lib 189 { 190 public: 191 /// Creates Gfx11Lib object CreateObj(const Client * pClient)192 static Addr::Lib* CreateObj(const Client* pClient) 193 { 194 VOID* pMem = Object::ClientAlloc(sizeof(Gfx11Lib), pClient); 195 return (pMem != NULL) ? new (pMem) Gfx11Lib(pClient) : NULL; 196 } 197 198 protected: 199 Gfx11Lib(const Client* pClient); 200 virtual ~Gfx11Lib(); 201 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)202 virtual BOOL_32 HwlIsStandardSwizzle( 203 AddrResourceType resourceType, 204 AddrSwizzleMode swizzleMode) const 205 { 206 return m_swizzleModeTable[swizzleMode].isStd; 207 } 208 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)209 virtual BOOL_32 HwlIsDisplaySwizzle( 210 AddrResourceType resourceType, 211 AddrSwizzleMode swizzleMode) const 212 { 213 return m_swizzleModeTable[swizzleMode].isDisp; 214 } 215 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)216 virtual BOOL_32 HwlIsThin( 217 AddrResourceType resourceType, 218 AddrSwizzleMode swizzleMode) const 219 { 220 return ((IsTex1d(resourceType) == TRUE) || 221 (IsTex2d(resourceType) == TRUE) || 222 ((IsTex3d(resourceType) == TRUE) && 223 (m_swizzleModeTable[swizzleMode].isStd == FALSE) && 224 (m_swizzleModeTable[swizzleMode].isDisp == FALSE))); 225 } 226 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)227 virtual BOOL_32 HwlIsThick( 228 AddrResourceType resourceType, 229 AddrSwizzleMode swizzleMode) const 230 { 231 return ((IsTex3d(resourceType) == TRUE) && 232 (m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp)); 233 } 234 235 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 236 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 237 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 238 239 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 240 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 241 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 242 243 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 244 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 245 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 246 247 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 248 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 249 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 250 251 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 252 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn); 253 254 virtual VOID HwlComputeDccAddrFromCoord( 255 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 256 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 257 258 virtual UINT_32 HwlGetEquationIndex( 259 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 260 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 261 HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)262 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 263 { 264 *ppEquationTable = m_equationTable; 265 266 return m_numEquations; 267 } 268 269 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 270 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 271 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const; 272 273 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 274 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 275 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const; 276 277 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 278 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 279 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const; 280 281 virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView( 282 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 283 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const; 284 285 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 286 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 287 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 288 289 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 290 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 291 292 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 293 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 294 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 295 296 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 297 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 298 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 299 300 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 301 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 302 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 303 304 virtual UINT_32 HwlComputeMaxBaseAlignments() const; 305 306 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const; 307 308 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn); 309 310 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 311 312 private: 313 // Initialize equation table 314 VOID InitEquationTable(); 315 316 ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled( 317 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 318 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 319 320 ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled( 321 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 322 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 323 324 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled( 325 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 326 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 327 328 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled( 329 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 330 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 331 332 UINT_32 ComputeOffsetFromSwizzlePattern( 333 const UINT_64* pPattern, 334 UINT_32 numBits, 335 UINT_32 x, 336 UINT_32 y, 337 UINT_32 z, 338 UINT_32 s) const; 339 340 UINT_32 ComputeOffsetFromEquation( 341 const ADDR_EQUATION* pEq, 342 UINT_32 x, 343 UINT_32 y, 344 UINT_32 z) const; 345 346 ADDR_E_RETURNCODE ComputeStereoInfo( 347 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 348 UINT_32* pAlignY, 349 UINT_32* pRightXor) const; 350 351 static void GetMipSize( 352 UINT_32 mip0Width, 353 UINT_32 mip0Height, 354 UINT_32 mip0Depth, 355 UINT_32 mipId, 356 UINT_32* pMipWidth, 357 UINT_32* pMipHeight, 358 UINT_32* pMipDepth = NULL) 359 { 360 *pMipWidth = ShiftCeil(Max(mip0Width, 1u), mipId); 361 *pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId); 362 363 if (pMipDepth != NULL) 364 { 365 *pMipDepth = ShiftCeil(Max(mip0Depth, 1u), mipId); 366 } 367 } 368 369 const ADDR_SW_PATINFO* GetSwizzlePatternInfo( 370 AddrSwizzleMode swizzleMode, 371 AddrResourceType resourceType, 372 UINT_32 log2Elem, 373 UINT_32 numFrag) const; 374 GetSwizzlePatternFromPatternInfo(const ADDR_SW_PATINFO * pPatInfo,ADDR_BIT_SETTING (& pSwizzle)[20])375 VOID GetSwizzlePatternFromPatternInfo( 376 const ADDR_SW_PATINFO* pPatInfo, 377 ADDR_BIT_SETTING (&pSwizzle)[20]) const 378 { 379 memcpy(pSwizzle, 380 GFX11_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx], 381 sizeof(GFX11_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx])); 382 383 memcpy(&pSwizzle[8], 384 GFX11_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx], 385 sizeof(GFX11_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx])); 386 387 memcpy(&pSwizzle[12], 388 GFX11_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx], 389 sizeof(GFX11_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx])); 390 391 memcpy(&pSwizzle[16], 392 GFX11_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx], 393 sizeof(GFX11_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx])); 394 } 395 396 VOID ConvertSwizzlePatternToEquation( 397 UINT_32 elemLog2, 398 AddrResourceType rsrcType, 399 AddrSwizzleMode swMode, 400 const ADDR_SW_PATINFO* pPatInfo, 401 ADDR_EQUATION* pEquation) const; 402 403 static INT_32 GetMetaElementSizeLog2(Gfx11DataType dataType); 404 405 static INT_32 GetMetaCacheSizeLog2(Gfx11DataType dataType); 406 407 void GetBlk256SizeLog2( 408 AddrResourceType resourceType, 409 AddrSwizzleMode swizzleMode, 410 UINT_32 elemLog2, 411 UINT_32 numSamplesLog2, 412 Dim3d* pBlock) const; 413 414 void GetCompressedBlockSizeLog2( 415 Gfx11DataType dataType, 416 AddrResourceType resourceType, 417 AddrSwizzleMode swizzleMode, 418 UINT_32 elemLog2, 419 UINT_32 numSamplesLog2, 420 Dim3d* pBlock) const; 421 422 INT_32 GetMetaOverlapLog2( 423 Gfx11DataType dataType, 424 AddrResourceType resourceType, 425 AddrSwizzleMode swizzleMode, 426 UINT_32 elemLog2, 427 UINT_32 numSamplesLog2) const; 428 429 INT_32 Get3DMetaOverlapLog2( 430 AddrResourceType resourceType, 431 AddrSwizzleMode swizzleMode, 432 UINT_32 elemLog2) const; 433 434 UINT_32 GetMetaBlkSize( 435 Gfx11DataType dataType, 436 AddrResourceType resourceType, 437 AddrSwizzleMode swizzleMode, 438 UINT_32 elemLog2, 439 UINT_32 numSamplesLog2, 440 BOOL_32 pipeAlign, 441 Dim3d* pBlock) const; 442 443 INT_32 GetPipeRotateAmount( 444 AddrResourceType resourceType, 445 AddrSwizzleMode swizzleMode) const; 446 GetEffectiveNumPipes()447 INT_32 GetEffectiveNumPipes() const 448 { 449 return ((m_numSaLog2 + 1) >= m_pipesLog2) ? m_pipesLog2 : m_numSaLog2 + 1; 450 } 451 IsRbAligned(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)452 BOOL_32 IsRbAligned( 453 AddrResourceType resourceType, 454 AddrSwizzleMode swizzleMode) const 455 { 456 const BOOL_32 isRtopt = IsRtOptSwizzle(swizzleMode); 457 const BOOL_32 isZ = IsZOrderSwizzle(swizzleMode); 458 const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode); 459 460 return (IsTex2d(resourceType) && (isRtopt || isZ)) || 461 (IsTex3d(resourceType) && isDisplay); 462 463 } 464 465 UINT_32 GetValidDisplaySwizzleModes(UINT_32 bpp) const; 466 467 BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 468 469 UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const; 470 GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet,AddrResourceType rsrcType)471 static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType) 472 { 473 ADDR2_BLOCK_SET allowedBlockSet = {}; 474 475 allowedBlockSet.micro = (allowedSwModeSet.value & Gfx11Blk256BSwModeMask) ? TRUE : FALSE; 476 allowedBlockSet.linear = (allowedSwModeSet.value & Gfx11LinearSwModeMask) ? TRUE : FALSE; 477 478 if (rsrcType == ADDR_RSRC_TEX_3D) 479 { 480 allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx11Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE; 481 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx11Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE; 482 allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx11Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE; 483 allowedBlockSet.gfx11.thin256KB = (allowedSwModeSet.value & Gfx11Rsrc3dThin256KBSwModeMask) ? TRUE : FALSE; 484 allowedBlockSet.gfx11.thick256KB = (allowedSwModeSet.value & Gfx11Rsrc3dThick256KBSwModeMask) ? TRUE : FALSE; 485 } 486 else 487 { 488 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx11Blk4KBSwModeMask) ? TRUE : FALSE; 489 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx11Blk64KBSwModeMask) ? TRUE : FALSE; 490 allowedBlockSet.gfx11.thin256KB = (allowedSwModeSet.value & Gfx11Blk256KBSwModeMask) ? TRUE : FALSE; 491 } 492 493 return allowedBlockSet; 494 } 495 GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)496 static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet) 497 { 498 ADDR2_SWTYPE_SET allowedSwSet = {}; 499 500 allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx11ZSwModeMask) ? TRUE : FALSE; 501 allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx11StandardSwModeMask) ? TRUE : FALSE; 502 allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx11DisplaySwModeMask) ? TRUE : FALSE; 503 allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx11RenderSwModeMask) ? TRUE : FALSE; 504 505 return allowedSwSet; 506 } 507 IsInMipTail(Dim3d mipTailDim,UINT_32 maxNumMipsInTail,UINT_32 mipWidth,UINT_32 mipHeight,UINT_32 numMipsToTheEnd)508 BOOL_32 IsInMipTail( 509 Dim3d mipTailDim, 510 UINT_32 maxNumMipsInTail, 511 UINT_32 mipWidth, 512 UINT_32 mipHeight, 513 UINT_32 numMipsToTheEnd) const 514 { 515 BOOL_32 inTail = ((mipWidth <= mipTailDim.w) && 516 (mipHeight <= mipTailDim.h) && 517 (numMipsToTheEnd <= maxNumMipsInTail)); 518 519 return inTail; 520 } 521 GetBankXorBits(UINT_32 blockBits)522 UINT_32 GetBankXorBits(UINT_32 blockBits) const 523 { 524 return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ? 525 Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0; 526 } 527 528 BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 529 BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 530 IsBlock256kb(AddrSwizzleMode swizzleMode)531 BOOL_32 IsBlock256kb(AddrSwizzleMode swizzleMode) const { return IsBlockVariable(swizzleMode); } 532 533 // TODO: figure out if there is any Column bits on GFX11... 534 static const UINT_32 ColumnBits = 2; 535 static const UINT_32 BankBits = 4; 536 static const UINT_32 UnalignedDccType = 3; 537 538 static const Dim3d Block256_3d[MaxNumOfBpp]; 539 static const Dim3d Block256K_Log2_3d[MaxNumOfBpp]; 540 static const Dim3d Block64K_Log2_3d[MaxNumOfBpp]; 541 static const Dim3d Block4K_Log2_3d[MaxNumOfBpp]; 542 543 static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE]; 544 545 // Number of packers log2 546 UINT_32 m_numPkrLog2; 547 // Number of shader array log2 548 UINT_32 m_numSaLog2; 549 550 Gfx11ChipSettings m_settings; 551 552 UINT_32 m_colorBaseIndex; 553 UINT_32 m_htileBaseIndex; 554 UINT_32 m_dccBaseIndex; 555 }; 556 557 } // V2 558 } // Addr 559 560 #endif 561 562