1 /* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12 #ifndef __ROCKCHIP_SIP_H
13 #define __ROCKCHIP_SIP_H
14
15 #include <linux/arm-smccc.h>
16 #include <linux/io.h>
17
18 /* SMC function IDs for SiP Service queries, compatible with kernel-3.10 */
19 #define SIP_ATF_VERSION 0x82000001
20 #define SIP_ACCESS_REG 0x82000002
21 #define SIP_SUSPEND_MODE 0x82000003
22 #define SIP_PENDING_CPUS 0x82000004
23 #define SIP_UARTDBG_CFG 0x82000005
24 #define SIP_UARTDBG_CFG64 0xc2000005
25 #define SIP_MCU_EL3FIQ_CFG 0x82000006
26 #define SIP_ACCESS_CHIP_STATE64 0xc2000006
27 #define SIP_SECURE_MEM_CONFIG 0x82000007
28 #define SIP_ACCESS_CHIP_EXTRA_STATE64 0xc2000007
29 #define SIP_DRAM_CONFIG 0x82000008
30 #define SIP_SHARE_MEM 0x82000009
31 #define SIP_SIP_VERSION 0x8200000a
32 #define SIP_REMOTECTL_CFG 0x8200000b
33 #define PSCI_SIP_VPU_RESET 0x8200000c
34 #define SIP_BUS_CFG 0x8200000d
35 #define SIP_LAST_LOG 0x8200000e
36 #define SIP_SCMI_AGENT0 0x82000010
37 #define SIP_SCMI_AGENT1 0x82000011
38 #define SIP_SCMI_AGENT2 0x82000012
39 #define SIP_SCMI_AGENT3 0x82000013
40 #define SIP_SCMI_AGENT4 0x82000014
41 #define SIP_SCMI_AGENT5 0x82000015
42 #define SIP_SCMI_AGENT6 0x82000016
43 #define SIP_SCMI_AGENT7 0x82000017
44 #define SIP_SCMI_AGENT8 0x82000018
45 #define SIP_SCMI_AGENT9 0x82000019
46 #define SIP_SCMI_AGENT10 0x8200001a
47 #define SIP_SCMI_AGENT11 0x8200001b
48 #define SIP_SCMI_AGENT12 0x8200001c
49 #define SIP_SCMI_AGENT13 0x8200001d
50 #define SIP_SCMI_AGENT14 0x8200001e
51 #define SIP_SCMI_AGENT15 0x8200001f
52 #define SIP_SDEI_FIQ_DBG_SWITCH_CPU 0x82000020
53 #define SIP_SDEI_FIQ_DBG_GET_EVENT_ID 0x82000021
54
55 /* Rockchip Sip version */
56 #define SIP_IMPLEMENT_V1 (1)
57 #define SIP_IMPLEMENT_V2 (2)
58
59 /* Trust firmware version */
60 #define ATF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
61 #define ATF_VER_MINOR(ver) (((ver) >> 0) & 0xffff)
62
63 /* SIP_ACCESS_REG: read or write */
64 #define SECURE_REG_RD 0x0
65 #define SECURE_REG_WR 0x1
66
67 /* Fiq debugger share memory: 8KB enough */
68 #define FIQ_UARTDBG_PAGE_NUMS 2
69 #define FIQ_UARTDBG_SHARE_MEM_SIZE ((FIQ_UARTDBG_PAGE_NUMS) * 4096)
70
71 /* Error return code */
72 #define IS_SIP_ERROR(x) (!!(x))
73
74 #define SIP_RET_SUCCESS 0
75 #define SIP_RET_SMC_UNKNOWN -1
76 #define SIP_RET_NOT_SUPPORTED -2
77 #define SIP_RET_INVALID_PARAMS -3
78 #define SIP_RET_INVALID_ADDRESS -4
79 #define SIP_RET_DENIED -5
80 #define SIP_RET_SET_RATE_TIMEOUT -6
81
82 /* SIP_UARTDBG_CFG64 call types */
83 #define UARTDBG_CFG_INIT 0xf0
84 #define UARTDBG_CFG_OSHDL_TO_OS 0xf1
85 #define UARTDBG_CFG_OSHDL_CPUSW 0xf3
86 #define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4
87 #define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5
88 #define UARTDBG_CFG_PRINT_PORT 0xf7
89 #define UARTDBG_CFG_FIQ_ENABEL 0xf8
90 #define UARTDBG_CFG_FIQ_DISABEL 0xf9
91
92 /* SIP_SUSPEND_MODE32 call types */
93 #define SUSPEND_MODE_CONFIG 0x01
94 #define WKUP_SOURCE_CONFIG 0x02
95 #define PWM_REGULATOR_CONFIG 0x03
96 #define GPIO_POWER_CONFIG 0x04
97 #define SUSPEND_DEBUG_ENABLE 0x05
98 #define APIOS_SUSPEND_CONFIG 0x06
99 #define VIRTUAL_POWEROFF 0x07
100 #define SUSPEND_WFI_TIME_MS 0x08
101 #define LINUX_PM_STATE 0x09
102
103 /* SIP_REMOTECTL_CFG call types */
104 #define REMOTECTL_SET_IRQ 0xf0
105 #define REMOTECTL_SET_PWM_CH 0xf1
106 #define REMOTECTL_SET_PWRKEY 0xf2
107 #define REMOTECTL_GET_WAKEUP_STATE 0xf3
108 #define REMOTECTL_ENABLE 0xf4
109 /* wakeup state */
110 #define REMOTECTL_PWRKEY_WAKEUP 0xdeadbeaf
111
112 struct dram_addrmap_info {
113 u64 ch_mask[2];
114 u64 bk_mask[4];
115 u64 bg_mask[2];
116 u64 cs_mask[2];
117 u32 reserved[20];
118 u32 bank_bit_first;
119 u32 bank_bit_mask;
120 };
121
122 enum {
123 FIRMWARE_NONE,
124 FIRMWARE_TEE_32BIT,
125 FIRMWARE_ATF_32BIT,
126 FIRMWARE_ATF_64BIT,
127 FIRMWARE_END,
128 };
129
130 /* Share mem page types */
131 typedef enum {
132 SHARE_PAGE_TYPE_INVALID = 0,
133 SHARE_PAGE_TYPE_UARTDBG,
134 SHARE_PAGE_TYPE_DDR,
135 SHARE_PAGE_TYPE_DDRDBG,
136 SHARE_PAGE_TYPE_DDRECC,
137 SHARE_PAGE_TYPE_DDRFSP,
138 SHARE_PAGE_TYPE_DDR_ADDRMAP,
139 SHARE_PAGE_TYPE_LAST_LOG,
140 SHARE_PAGE_TYPE_MAX,
141 } share_page_type_t;
142
143 /*
144 * Rules: struct arm_smccc_res contains result and data, details:
145 *
146 * a0: error code(0: success, !0: error);
147 * a1~a3: data
148 */
149 #if IS_ENABLED(CONFIG_ROCKCHIP_SIP)
150 struct arm_smccc_res sip_smc_get_atf_version(void);
151 struct arm_smccc_res sip_smc_get_sip_version(void);
152 struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2);
153 struct arm_smccc_res sip_smc_request_share_mem(u32 page_num,
154 share_page_type_t page_type);
155 struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2);
156 struct arm_smccc_res sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2);
157 struct arm_smccc_res sip_smc_get_suspend_info(u32 info);
158 struct arm_smccc_res sip_smc_lastlog_request(void);
159
160 int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2);
161 int sip_smc_virtual_poweroff(void);
162 int sip_smc_remotectl_config(u32 func, u32 data);
163
164 int sip_smc_secure_reg_write(u32 addr_phy, u32 val);
165 u32 sip_smc_secure_reg_read(u32 addr_phy);
166 struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2);
167 struct dram_addrmap_info *sip_smc_get_dram_map(void);
168
169 /***************************fiq debugger **************************************/
170 void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu);
171 void sip_fiq_debugger_enable_debug(bool enable);
172 int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback_fn);
173 int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate);
174 int sip_fiq_debugger_request_share_memory(void);
175 int sip_fiq_debugger_get_target_cpu(void);
176 int sip_fiq_debugger_switch_cpu(u32 cpu);
177 int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu, u32 flag);
178 int sip_fiq_debugger_is_enabled(void);
179 int sip_fiq_debugger_sdei_get_event_id(u32 *fiq, u32 *sw_cpu, u32 *flag);
180 #else
sip_smc_get_atf_version(void)181 static inline struct arm_smccc_res sip_smc_get_atf_version(void)
182 {
183 struct arm_smccc_res tmp = {0};
184 return tmp;
185 }
186
sip_smc_get_sip_version(void)187 static inline struct arm_smccc_res sip_smc_get_sip_version(void)
188 {
189 struct arm_smccc_res tmp = {0};
190 return tmp;
191 }
192
sip_smc_dram(u32 arg0,u32 arg1,u32 arg2)193 static inline struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2)
194 {
195 struct arm_smccc_res tmp = {0};
196 return tmp;
197 }
198
sip_smc_request_share_mem(u32 page_num,share_page_type_t page_type)199 static inline struct arm_smccc_res sip_smc_request_share_mem
200 (u32 page_num, share_page_type_t page_type)
201 {
202 struct arm_smccc_res tmp = {0};
203 return tmp;
204 }
205
sip_smc_mcu_el3fiq(u32 arg0,u32 arg1,u32 arg2)206 static inline struct arm_smccc_res sip_smc_mcu_el3fiq
207 (u32 arg0, u32 arg1, u32 arg2)
208 {
209 struct arm_smccc_res tmp = {0};
210 return tmp;
211 }
212
213 static inline struct arm_smccc_res
sip_smc_vpu_reset(u32 arg0,u32 arg1,u32 arg2)214 sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2)
215 {
216 struct arm_smccc_res tmp = {0};
217 return tmp;
218 }
219
sip_smc_lastlog_request(void)220 static inline struct arm_smccc_res sip_smc_lastlog_request(void)
221 {
222 struct arm_smccc_res tmp = {0};
223 return tmp;
224 }
225
sip_smc_set_suspend_mode(u32 ctrl,u32 config1,u32 config2)226 static inline int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2)
227 {
228 return 0;
229 }
230
sip_smc_get_suspend_info(u32 info)231 static inline int sip_smc_get_suspend_info(u32 info)
232 {
233 return 0;
234 }
235
sip_smc_virtual_poweroff(void)236 static inline int sip_smc_virtual_poweroff(void) { return 0; }
sip_smc_remotectl_config(u32 func,u32 data)237 static inline int sip_smc_remotectl_config(u32 func, u32 data) { return 0; }
sip_smc_secure_reg_read(u32 addr_phy)238 static inline u32 sip_smc_secure_reg_read(u32 addr_phy) { return 0; }
sip_smc_secure_reg_write(u32 addr_phy,u32 val)239 static inline int sip_smc_secure_reg_write(u32 addr_phy, u32 val) { return 0; }
sip_smc_soc_bus_div(u32 arg0,u32 arg1,u32 arg2)240 static inline int sip_smc_soc_bus_div(u32 arg0, u32 arg1, u32 arg2)
241 {
242 return 0;
243 }
sip_smc_get_dram_map(void)244 static inline struct dram_addrmap_info *sip_smc_get_dram_map(void)
245 {
246 return NULL;
247 }
248
249 /***************************fiq debugger **************************************/
sip_fiq_debugger_enable_fiq(bool enable,uint32_t tgt_cpu)250 static inline void sip_fiq_debugger_enable_fiq
251 (bool enable, uint32_t tgt_cpu) { return; }
252
sip_fiq_debugger_enable_debug(bool enable)253 static inline void sip_fiq_debugger_enable_debug(bool enable) { return; }
sip_fiq_debugger_uart_irq_tf_init(u32 irq_id,void * callback_fn)254 static inline int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id,
255 void *callback_fn)
256 {
257 return 0;
258 }
259
sip_fiq_debugger_set_print_port(u32 port_phyaddr,u32 baudrate)260 static inline int sip_fiq_debugger_set_print_port(u32 port_phyaddr,
261 u32 baudrate)
262 {
263 return 0;
264 }
265
sip_fiq_debugger_request_share_memory(void)266 static inline int sip_fiq_debugger_request_share_memory(void) { return 0; }
sip_fiq_debugger_get_target_cpu(void)267 static inline int sip_fiq_debugger_get_target_cpu(void) { return 0; }
sip_fiq_debugger_switch_cpu(u32 cpu)268 static inline int sip_fiq_debugger_switch_cpu(u32 cpu) { return 0; }
sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu,u32 target_cpu,u32 flag)269 static inline int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu,
270 u32 flag) { return 0; }
sip_fiq_debugger_is_enabled(void)271 static inline int sip_fiq_debugger_is_enabled(void) { return 0; }
272 #endif
273
274 /* 32-bit OP-TEE context, never change order of members! */
275 struct sm_nsec_ctx {
276 u32 usr_sp;
277 u32 usr_lr;
278 u32 irq_spsr;
279 u32 irq_sp;
280 u32 irq_lr;
281 u32 fiq_spsr;
282 u32 fiq_sp;
283 u32 fiq_lr;
284 u32 svc_spsr;
285 u32 svc_sp;
286 u32 svc_lr;
287 u32 abt_spsr;
288 u32 abt_sp;
289 u32 abt_lr;
290 u32 und_spsr;
291 u32 und_sp;
292 u32 und_lr;
293 u32 mon_lr;
294 u32 mon_spsr;
295 u32 r4;
296 u32 r5;
297 u32 r6;
298 u32 r7;
299 u32 r8;
300 u32 r9;
301 u32 r10;
302 u32 r11;
303 u32 r12;
304 u32 r0;
305 u32 r1;
306 u32 r2;
307 u32 r3;
308 };
309
310 /* 64-bit ATF context, never change order of members! */
311 struct gp_regs_ctx {
312 u64 x0;
313 u64 x1;
314 u64 x2;
315 u64 x3;
316 u64 x4;
317 u64 x5;
318 u64 x6;
319 u64 x7;
320 u64 x8;
321 u64 x9;
322 u64 x10;
323 u64 x11;
324 u64 x12;
325 u64 x13;
326 u64 x14;
327 u64 x15;
328 u64 x16;
329 u64 x17;
330 u64 x18;
331 u64 x19;
332 u64 x20;
333 u64 x21;
334 u64 x22;
335 u64 x23;
336 u64 x24;
337 u64 x25;
338 u64 x26;
339 u64 x27;
340 u64 x28;
341 u64 x29;
342 u64 lr;
343 u64 sp_el0;
344 u64 scr_el3;
345 u64 runtime_sp;
346 u64 spsr_el3;
347 u64 elr_el3;
348 };
349
350 #endif
351