Lines Matching full:operand
86 void AssemblerAarch64::Ldp(const Register &rt, const Register &rt2, const MemoryOperand &operand) in Ldp() argument
89 if (operand.IsImmediateOffset()) { in Ldp()
90 switch (operand.GetAddrMode()) { in Ldp()
105 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldp()
112 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldp()
120 void AssemblerAarch64::Stp(const Register &rt, const Register &rt2, const MemoryOperand &operand) in Stp() argument
123 if (operand.IsImmediateOffset()) { in Stp()
124 switch (operand.GetAddrMode()) { in Stp()
139 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stp()
146 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Stp()
154 …blerAarch64::Ldp(const VectorRegister &vt, const VectorRegister &vt2, const MemoryOperand &operand) in Ldp() argument
157 if (operand.IsImmediateOffset()) { in Ldp()
158 switch (operand.GetAddrMode()) { in Ldp()
172 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldp()
192 Rn(operand.GetRegBase().GetId()) | Rt(vt.GetId()); in Ldp()
200 …blerAarch64::Stp(const VectorRegister &vt, const VectorRegister &vt2, const MemoryOperand &operand) in Stp() argument
203 if (operand.IsImmediateOffset()) { in Stp()
204 switch (operand.GetAddrMode()) { in Stp()
218 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stp()
238 Rn(operand.GetRegBase().GetId()) | Rt(vt.GetId()); in Stp()
273 void AssemblerAarch64::Ldr(const Register &rt, const MemoryOperand &operand, Scale scale) in Ldr() argument
276 uint32_t op = GetOpcodeOfLdr(operand, scale); in Ldr()
277 if (operand.IsImmediateOffset()) { in Ldr()
278 uint64_t imm = GetImmOfLdr(operand, scale, regX); in Ldr()
279 bool isSigned = operand.GetAddrMode() != AddrMode::OFFSET; in Ldr()
282 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldr()
285 ASSERT(operand.GetExtendOption() != Extend::NO_EXTEND); in Ldr()
286 uint32_t shift = GetShiftOfLdr(operand, scale, regX); in Ldr()
287 Register rm = operand.GetRegisterOffset(); in Ldr()
288 Register rn = operand.GetRegBase(); in Ldr()
290 (operand.GetExtendOption() << LDR_STR_Extend_LOWBITS) & LDR_STR_Extend_MASK; in Ldr()
299 void AssemblerAarch64::Ldr(const Register &rt, const MemoryOperand &operand) in Ldr() argument
301 Ldr(rt, operand, Scale::Q); in Ldr()
304 void AssemblerAarch64::Ldrh(const Register &rt, const MemoryOperand &operand) in Ldrh() argument
307 Ldr(rt, operand, Scale::H); in Ldrh()
310 void AssemblerAarch64::Ldrb(const Register &rt, const MemoryOperand &operand) in Ldrb() argument
313 Ldr(rt, operand, Scale::B); in Ldrb()
316 void AssemblerAarch64::Str(const Register &rt, const MemoryOperand &operand) in Str() argument
321 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Str()
322 if (operand.IsImmediateOffset()) { in Str()
323 switch (operand.GetAddrMode()) { in Str()
345 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Str()
353 void AssemblerAarch64::Ldur(const Register &rt, const MemoryOperand &operand) in Ldur() argument
357 ASSERT(operand.IsImmediateOffset()); in Ldur()
358 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Ldur()
361 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Ldur()
365 void AssemblerAarch64::Stur(const Register &rt, const MemoryOperand &operand) in Stur() argument
369 ASSERT(operand.IsImmediateOffset()); in Stur()
370 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in Stur()
373 Rn(operand.GetRegBase().GetId()) | Rt(rt.GetId()); in Stur()
458 Add(rd, rm, Operand(Immediate(0))); in Mov()
460 Orr(rd, Register(Zero), Operand(rm)); in Mov()
629 …firstshift = (tz / 16) * 16; // 16 : 16 means the operand of MOVK/N/Z is 16 bits Immediate in EmitMovInstruct()
631 …lastshift = ((63 - lz) / 16) * 16; // 16 : 16 means the operand of MOVK/N/Z is 16 bits Immediate in EmitMovInstruct()
644 … firstshift += 16; // 16 : 16 means the operand of MOVK is 16 bits Immediate in EmitMovInstruct()
693 void AssemblerAarch64::Orr(const Register &rd, const Register &rn, const Operand &operand) in Orr() argument
695 ASSERT(operand.IsShifted()); in Orr()
696 BitWiseOpShift(ORR_Shift, rd, rn, operand); in Orr()
699 void AssemblerAarch64::And(const Register &rd, const Register &rn, const Operand &operand) in And() argument
701 ASSERT(operand.IsShifted()); in And()
702 BitWiseOpShift(AND_Shift, rd, rn, operand); in And()
705 void AssemblerAarch64::Ands(const Register &rd, const Register &rn, const Operand &operand) in Ands() argument
707 ASSERT(operand.IsShifted()); in Ands()
708 BitWiseOpShift(ANDS_Shift, rd, rn, operand); in Ands()
717 …4::BitWiseOpShift(BitwiseOpCode op, const Register &rd, const Register &rn, const Operand &operand) in BitWiseOpShift() argument
719 …uint32_t shift_field = (operand.GetShiftOption() << BITWISE_OP_Shift_LOWBITS) & BITWISE_OP_Shift_M… in BitWiseOpShift()
720 …uint32_t shift_amount = (operand.GetShiftAmount() << BITWISE_OP_ShiftAmount_LOWBITS) & BITWISE_OP_… in BitWiseOpShift()
721 uint32_t code = Sf(!rd.IsW()) | op | shift_field | Rm(operand.Reg().GetId()) | in BitWiseOpShift()
773 void AssemblerAarch64::Add(const Register &rd, const Register &rn, const Operand &operand) in Add() argument
775 if (operand.IsImmediate()) { in Add()
776 int64_t imm = static_cast<int64_t>(operand.ImmediateValue()); in Add()
783 if (operand.IsShifted()) { in Add()
784 AddSubReg(ADD_Shift, rd, rn, false, operand); in Add()
786 AddSubReg(ADD_Extend, rd, rn, false, operand); in Add()
791 void AssemblerAarch64::Adds(const Register &rd, const Register &rn, const Operand &operand) in Adds() argument
793 if (operand.IsImmediate()) { in Adds()
794 AddSubImm(ADD_Imm, rd, rn, true, operand.ImmediateValue()); in Adds()
796 if (operand.IsShifted()) { in Adds()
797 AddSubReg(ADD_Shift, rd, rn, true, operand); in Adds()
799 AddSubReg(ADD_Extend, rd, rn, true, operand); in Adds()
804 void AssemblerAarch64::Sub(const Register &rd, const Register &rn, const Operand &operand) in Sub() argument
806 if (operand.IsImmediate()) { in Sub()
807 int64_t imm = static_cast<int64_t>(operand.ImmediateValue()); in Sub()
814 if (operand.IsShifted()) { in Sub()
815 AddSubReg(SUB_Shift, rd, rn, false, operand); in Sub()
817 AddSubReg(SUB_Extend, rd, rn, false, operand); in Sub()
822 void AssemblerAarch64::Subs(const Register &rd, const Register &rn, const Operand &operand) in Subs() argument
824 if (operand.IsImmediate()) { in Subs()
825 AddSubImm(SUB_Imm, rd, rn, true, operand.ImmediateValue()); in Subs()
827 if (operand.IsShifted()) { in Subs()
828 AddSubReg(SUB_Shift, rd, rn, true, operand); in Subs()
830 AddSubReg(SUB_Extend, rd, rn, true, operand); in Subs()
867 bool setFlags, const Operand &operand) in AddSubReg() argument
871 if (operand.IsShifted()) { in AddSubReg()
872 … uint32_t shift_field = ((operand.GetShiftOption()) << ADD_SUB_Shift_LOWBITS) & ADD_SUB_Shift_MASK; in AddSubReg()
873 …uint32_t shift_amount = ((operand.GetShiftAmount()) << ADD_SUB_ShiftAmount_LOWBITS) & ADD_SUB_Shif… in AddSubReg()
875 code = Sf(!rd.IsW()) | op | flags_field | shift_field | Rm(operand.Reg().GetId()) | in AddSubReg()
880 (operand.GetExtendOption() << ADD_SUB_ExtendOption_LOWBITS) & ADD_SUB_ExtendOption_MASK; in AddSubReg()
881 …uint32_t extend_shift = (operand.GetShiftAmount() << ADD_SUB_ExtendShift_LOWBITS) & ADD_SUB_Extend… in AddSubReg()
882 code = Sf(!rd.IsW()) | op | flags_field | Rm(operand.Reg().GetId()) | extend_field | in AddSubReg()
888 void AssemblerAarch64::Cmp(const Register &rd, const Operand &operand) in Cmp() argument
890 Subs(Register(Zero, rd.GetType()), rd, operand); in Cmp()
893 void AssemblerAarch64::CMov(const Register &rd, const Register &rn, const Operand &operand, Conditi… in CMov() argument
895 ASSERT(!operand.IsImmediate()); in CMov()
897 …uint32_t code = Sf(!rd.IsW()) | CSEL | Rm(operand.Reg().GetId()) | cond_field | Rn(rn.GetId()) | R… in CMov()
1018 void AssemblerAarch64::Tst(const Register& rn, const Operand& operand) in Tst() argument
1020 Ands(Register(Zero, rn.GetType()), rn, operand); in Tst()
1145 uint64_t AssemblerAarch64::GetImmOfLdr(const MemoryOperand &operand, Scale scale, bool isRegX) in GetImmOfLdr() argument
1147 ASSERT(operand.IsImmediateOffset()); in GetImmOfLdr()
1148 uint64_t imm = static_cast<uint64_t>(operand.GetImmediate().Value()); in GetImmOfLdr()
1149 if (operand.GetAddrMode() == OFFSET) { in GetImmOfLdr()
1163 uint64_t AssemblerAarch64::GetOpcodeOfLdr(const MemoryOperand &operand, Scale scale) in GetOpcodeOfLdr() argument
1166 if (operand.IsImmediateOffset()) { in GetOpcodeOfLdr()
1167 switch (operand.GetAddrMode()) { in GetOpcodeOfLdr()
1226 uint32_t AssemblerAarch64::GetShiftOfLdr(const MemoryOperand &operand, Scale scale, bool isRegX) in GetShiftOfLdr() argument
1230 shift = operand.GetShiftOption() != Shift::NO_SHIFT; in GetShiftOfLdr()
1232 shift = operand.GetShiftAmount(); in GetShiftOfLdr()
1236 shift = operand.GetShiftAmount(); in GetShiftOfLdr()