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Lines Matching full:acc

47     GateAccessor acc(const_cast<Circuit*>(circuit));  in CalculateDominatorTree()  local
54 auto startGate = acc.GetStateRoot(); in CalculateDominatorTree()
55 acc.SetMark(startGate, MarkCode::VISITED); in CalculateDominatorTree()
62 if (acc.GetOpCode(curGate) != OpCode::LOOP_BACK) { in CalculateDominatorTree()
63 auto uses = acc.Uses(curGate); in CalculateDominatorTree()
65 if (useIt.GetIndex() < acc.GetStateCount(*useIt) && in CalculateDominatorTree()
66 acc.IsState(*useIt) && acc.GetMark(*useIt) == MarkCode::NO_MARK) { in CalculateDominatorTree()
67 acc.SetMark(*useIt, MarkCode::VISITED); in CalculateDominatorTree()
95 acc.GetInStates(bbGatesList[idx], preGates); in CalculateDominatorTree()
131 GateAccessor acc(const_cast<Circuit*>(circuit)); in Run() local
213 acc.GetOuts(acc.GetArgRoot(), argList); in Run()
215 return acc.TryGetValue(lhs) > acc.TryGetValue(rhs); in Run()
221 auto uses = acc.Uses(bbGate); in Run()
224 if (acc.IsFixed(succGate)) { in Run()
225 result[bbGatesAddrToIdx.at(acc.GetIn(succGate, 0))].push_back(succGate); in Run()
241 GateAccessor acc(const_cast<Circuit*>(circuit)); in CalculateSchedulingUpperBound() local
256 } else if (acc.IsProlog(gate) || acc.IsRoot(gate) || acc.IsVirtualState(gate)) { in CalculateSchedulingUpperBound()
259 } else if (acc.IsFixed(gate)) { in CalculateSchedulingUpperBound()
260 returnValue = bbGatesAddrToIdx.at(acc.GetIn(gate, 0)); in CalculateSchedulingUpperBound()
262 } else if (acc.IsState(gate)) { in CalculateSchedulingUpperBound()
281 acc.GetIns(schedulableGate, rootPredGates); in CalculateSchedulingUpperBound()
320 acc.GetIns(predGate, newPredGates); in CalculateSchedulingUpperBound()
345 GateAccessor acc(const_cast<Circuit*>(circuit)); in CalculateFixedGatesList() local
348 auto uses = acc.Uses(item.first); in CalculateFixedGatesList()
351 if (acc.IsFixed(succGate)) { in CalculateFixedGatesList()
364 GateAccessor acc(const_cast<Circuit*>(circuit)); in CalculateSchedulingLowerBound() local
378 acc.GetIns(gate, rootPrevGates); in CalculateSchedulingLowerBound()
388 if (!acc.IsSchedulable(prevGate)) { in CalculateSchedulingLowerBound()
397 acc.GetIns(prevGate, newPrevGates); in CalculateSchedulingLowerBound()
414 acc.GetIns(gate, rootPrevGates); in CalculateSchedulingLowerBound()
425 if (!acc.IsSchedulable(prevGate)) { in CalculateSchedulingLowerBound()
431 if (acc.IsState(curGate)) { // cur_opcode would not be STATE_ENTRY in CalculateSchedulingLowerBound()
433 } else if (acc.IsSelector(curGate)) { in CalculateSchedulingLowerBound()
435 curLowerBound = bbGatesAddrToIdx.at(acc.GetIn(acc.GetIn(curGate, 0), idx - 1)); in CalculateSchedulingLowerBound()
436 } else if (acc.IsFixed(curGate)) { in CalculateSchedulingLowerBound()
438 curLowerBound = bbGatesAddrToIdx.at(acc.GetIn(curGate, 0)); in CalculateSchedulingLowerBound()
455 acc.GetIns(prevGate, newPrevGates); in CalculateSchedulingLowerBound()
464 GateAccessor acc(const_cast<Circuit*>(circuit)); in Print() local
471 auto opcode = acc.GetOpCode((*cfg)[bbIdx].front()); in Print()
477 auto ins = acc.Ins(head); in Print()
480 if (acc.IsState(predState) || in Print()
481 acc.GetOpCode(predState) == OpCode::STATE_ENTRY) { in Print()
489 auto uses = acc.Uses(h); in Print()
492 if (acc.IsState(succState) || in Print()
493 acc.GetOpCode(succState) == OpCode::STATE_ENTRY) { in Print()
500 acc.Print((*cfg)[bbIdx][instIdx - 1]); in Print()