Lines Matching +full:non +full:- +full:contiguous

1 .. SPDX-License-Identifier: GPL-2.0
11 spans a contiguous range up to the maximal address. It could be,
13 for the CPU. Then there could be several contiguous ranges at
29 Regardless of the selected memory model, there exists one-to-one
41 non-NUMA systems with contiguous, or mostly contiguous, physical
60 straightforward: `PFN - ARCH_PFN_OFFSET` is an index to the
82 Every `node_mem_map` behaves exactly as FLATMEM's `mem_map` -
96 page->flags.
108 as hot-plug and hot-remove of the physical memory, alternative memory
109 maps for non-volatile memory devices and deferred initialization of
128    NR\_MEM\_SECTIONS = 2 ^ {(MAX\_PHYSMEM\_BITS - SECTION\_SIZE\_BITS)}
130 The `mem_section` objects are arranged in a two-dimensional array
147 corresponding `struct page` - a "classic sparse" and "sparse
151 The classic sparse encodes the section number of a page in page->flags
157 page *vmemmap` pointer that points to a virtually contiguous array of
173 for persistent memory devices in pre-allocated storage on those
201 this lack of user-api constraint to allow sub-section sized memory
202 ranges to be specified to :c:func:`arch_add_memory`, the top-half of
203 memory hotplug. Sub-section support allows for 2MB as the cross-arch
208 * pmem: Map platform persistent memory to be used as a direct-I/O target
211 * hmm: Extend `ZONE_DEVICE` with `->page_fault()` and `->page_free()`
212   event callbacks to allow a device-driver to coordinate memory management
213   events related to device-memory, typically GPU memory. See
217   PCI/-E topology to coordinate direct-DMA operations between themselves,