Lines Matching +full:snvs +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
58 #size-cells = <0>;
61 compatible = "arm,cortex-a7";
64 clock-frequency = <696000000>;
65 clock-latency = <61036>; /* two CLK32 periods */
66 #cooling-cells = <2>;
67 operating-points =
73 fsl,soc-operating-points =
86 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
89 arm-supply = <®_arm>;
90 soc-supply = <®_soc>;
91 nvmem-cells = <&cpu_speed_grade>;
92 nvmem-cell-names = "speed_grade";
97 compatible = "arm,armv7-timer";
102 interrupt-parent = <&intc>;
106 ckil: clock-cli {
107 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <32768>;
110 clock-output-names = "ckil";
113 osc: clock-osc {
114 compatible = "fixed-clock";
115 #clock-cells = <0>;
116 clock-frequency = <24000000>;
117 clock-output-names = "osc";
120 ipp_di0: clock-di0 {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <0>;
124 clock-output-names = "ipp_di0";
127 ipp_di1: clock-di1 {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <0>;
131 clock-output-names = "ipp_di1";
135 compatible = "arm,cortex-a7-pmu";
136 interrupt-parent = <&gpc>;
141 #address-cells = <1>;
142 #size-cells = <1>;
143 compatible = "simple-bus";
144 interrupt-parent = <&gpc>;
148 compatible = "mmio-sram";
151 #address-cells = <1>;
152 #size-cells = <1>;
155 intc: interrupt-controller@a01000 {
156 compatible = "arm,gic-400", "arm,cortex-a7-gic";
158 #interrupt-cells = <3>;
159 interrupt-controller;
160 interrupt-parent = <&intc>;
167 dma_apbh: dma-controller@1804000 {
168 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
174 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
175 #dma-cells = <1>;
176 dma-channels = <4>;
180 gpmi: nand-controller@1806000 {
181 compatible = "fsl,imx6q-gpmi-nand";
182 #address-cells = <1>;
183 #size-cells = <1>;
185 reg-names = "gpmi-nand", "bch";
187 interrupt-names = "bch";
193 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
196 dma-names = "rx-tx";
201 compatible = "fsl,aips-bus", "simple-bus";
202 #address-cells = <1>;
203 #size-cells = <1>;
207 spba-bus@2000000 {
208 compatible = "fsl,spba-bus", "simple-bus";
209 #address-cells = <1>;
210 #size-cells = <1>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
222 clock-names = "ipg", "per";
224 dma-names = "rx", "tx";
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
236 clock-names = "ipg", "per";
238 dma-names = "rx", "tx";
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
250 clock-names = "ipg", "per";
252 dma-names = "rx", "tx";
257 #address-cells = <1>;
258 #size-cells = <0>;
259 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
264 clock-names = "ipg", "per";
266 dma-names = "rx", "tx";
271 compatible = "fsl,imx6ul-uart",
272 "fsl,imx6q-uart";
277 clock-names = "ipg", "per";
282 compatible = "fsl,imx6ul-uart",
283 "fsl,imx6q-uart";
288 clock-names = "ipg", "per";
293 compatible = "fsl,imx6ul-uart",
294 "fsl,imx6q-uart";
299 clock-names = "ipg", "per";
304 #sound-dai-cells = <0>;
305 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
311 clock-names = "bus", "mclk1", "mclk2", "mclk3";
314 dma-names = "rx", "tx";
319 #sound-dai-cells = <0>;
320 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
326 clock-names = "bus", "mclk1", "mclk2", "mclk3";
329 dma-names = "rx", "tx";
334 #sound-dai-cells = <0>;
335 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
341 clock-names = "bus", "mclk1", "mclk2", "mclk3";
344 dma-names = "rx", "tx";
349 compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc";
359 clock-names = "mem", "ipg", "asrck_0",
366 dma-names = "rxa", "rxb", "rxc",
368 fsl,asrc-rate = <48000>;
369 fsl,asrc-width = <16>;
375 compatible = "fsl,imx6ul-tsc";
381 clock-names = "tsc", "adc";
386 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
391 clock-names = "ipg", "per";
392 #pwm-cells = <3>;
397 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
402 clock-names = "ipg", "per";
403 #pwm-cells = <3>;
408 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
413 clock-names = "ipg", "per";
414 #pwm-cells = <3>;
419 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
424 clock-names = "ipg", "per";
425 #pwm-cells = <3>;
430 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
435 clock-names = "ipg", "per";
436 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
441 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
446 clock-names = "ipg", "per";
447 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
452 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
457 clock-names = "ipg", "per";
461 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
466 gpio-controller;
467 #gpio-cells = <2>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
475 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
480 gpio-controller;
481 #gpio-cells = <2>;
482 interrupt-controller;
483 #interrupt-cells = <2>;
484 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
488 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
493 gpio-controller;
494 #gpio-cells = <2>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 gpio-ranges = <&iomuxc 0 65 29>;
501 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
506 gpio-controller;
507 #gpio-cells = <2>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
514 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
519 gpio-controller;
520 #gpio-cells = <2>;
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
527 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
529 interrupt-names = "int0", "pps";
537 clock-names = "ipg", "ahb", "ptp",
539 fsl,num-tx-queues = <1>;
540 fsl,num-rx-queues = <1>;
541 fsl,stop-mode = <&gpr 0x10 4>;
546 compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
554 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
561 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
568 clks: clock-controller@20c4000 {
569 compatible = "fsl,imx6ul-ccm";
573 #clock-cells = <1>;
575 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
579 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
580 "syscon", "simple-mfd";
586 reg_3p0: regulator-3p0 {
587 compatible = "fsl,anatop-regulator";
588 regulator-name = "vdd3p0";
589 regulator-min-microvolt = <2625000>;
590 regulator-max-microvolt = <3400000>;
591 anatop-reg-offset = <0x120>;
592 anatop-vol-bit-shift = <8>;
593 anatop-vol-bit-width = <5>;
594 anatop-min-bit-val = <0>;
595 anatop-min-voltage = <2625000>;
596 anatop-max-voltage = <3400000>;
597 anatop-enable-bit = <0>;
600 reg_arm: regulator-vddcore {
601 compatible = "fsl,anatop-regulator";
602 regulator-name = "cpu";
603 regulator-min-microvolt = <725000>;
604 regulator-max-microvolt = <1450000>;
605 regulator-always-on;
606 anatop-reg-offset = <0x140>;
607 anatop-vol-bit-shift = <0>;
608 anatop-vol-bit-width = <5>;
609 anatop-delay-reg-offset = <0x170>;
610 anatop-delay-bit-shift = <24>;
611 anatop-delay-bit-width = <2>;
612 anatop-min-bit-val = <1>;
613 anatop-min-voltage = <725000>;
614 anatop-max-voltage = <1450000>;
617 reg_soc: regulator-vddsoc {
618 compatible = "fsl,anatop-regulator";
619 regulator-name = "vddsoc";
620 regulator-min-microvolt = <725000>;
621 regulator-max-microvolt = <1450000>;
622 regulator-always-on;
623 anatop-reg-offset = <0x140>;
624 anatop-vol-bit-shift = <18>;
625 anatop-vol-bit-width = <5>;
626 anatop-delay-reg-offset = <0x170>;
627 anatop-delay-bit-shift = <28>;
628 anatop-delay-bit-width = <2>;
629 anatop-min-bit-val = <1>;
630 anatop-min-voltage = <725000>;
631 anatop-max-voltage = <1450000>;
635 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
636 interrupt-parent = <&gpc>;
639 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
640 nvmem-cell-names = "calib", "temp_grade";
646 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
650 phy-3p0-supply = <®_3p0>;
655 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
659 phy-3p0-supply = <®_3p0>;
663 snvs: snvs@20cc000 { label
664 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
667 snvs_rtc: snvs-rtc-lp {
668 compatible = "fsl,sec-v4.0-mon-rtc-lp";
669 regmap = <&snvs>;
675 snvs_poweroff: snvs-poweroff {
676 compatible = "syscon-poweroff";
677 regmap = <&snvs>;
684 snvs_pwrkey: snvs-powerkey {
685 compatible = "fsl,sec-v4.0-pwrkey";
686 regmap = <&snvs>;
689 wakeup-source;
693 snvs_lpgpr: snvs-lpgpr {
694 compatible = "fsl,imx6ul-snvs-lpgpr";
708 src: reset-controller@20d8000 {
709 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
713 #reset-cells = <1>;
717 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
719 interrupt-controller;
720 #interrupt-cells = <3>;
722 interrupt-parent = <&intc>;
726 compatible = "fsl,imx6ul-iomuxc";
730 gpr: iomuxc-gpr@20e4000 {
731 compatible = "fsl,imx6ul-iomuxc-gpr",
732 "fsl,imx6q-iomuxc-gpr", "syscon";
737 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
742 clock-names = "ipg", "per";
746 sdma: dma-controller@20ec000 {
747 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
748 "fsl,imx35-sdma";
753 clock-names = "ipg", "ahb";
754 #dma-cells = <3>;
755 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
759 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
764 clock-names = "ipg", "per";
765 #pwm-cells = <3>;
770 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
775 clock-names = "ipg", "per";
776 #pwm-cells = <3>;
781 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
786 clock-names = "ipg", "per";
787 #pwm-cells = <3>;
792 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
797 clock-names = "ipg", "per";
798 #pwm-cells = <3>;
804 compatible = "fsl,aips-bus", "simple-bus";
805 #address-cells = <1>;
806 #size-cells = <1>;
811 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
812 #address-cells = <1>;
813 #size-cells = <1>;
819 clock-names = "ipg", "aclk", "mem";
822 compatible = "fsl,sec-v4.0-job-ring";
828 compatible = "fsl,sec-v4.0-job-ring";
834 compatible = "fsl,sec-v4.0-job-ring";
841 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
848 ahb-burst-config = <0x0>;
849 tx-burst-size-dword = <0x10>;
850 rx-burst-size-dword = <0x10>;
855 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
861 ahb-burst-config = <0x0>;
862 tx-burst-size-dword = <0x10>;
863 rx-burst-size-dword = <0x10>;
868 #index-cells = <1>;
869 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
874 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
876 interrupt-names = "int0", "pps";
884 clock-names = "ipg", "ahb", "ptp",
886 fsl,num-tx-queues = <1>;
887 fsl,num-rx-queues = <1>;
888 fsl,stop-mode = <&gpr 0x10 3>;
893 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
899 clock-names = "ipg", "ahb", "per";
900 fsl,tuning-step = <2>;
901 fsl,tuning-start-tap = <20>;
902 bus-width = <4>;
907 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
913 clock-names = "ipg", "ahb", "per";
914 bus-width = <4>;
915 fsl,tuning-step = <2>;
916 fsl,tuning-start-tap = <20>;
921 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
925 num-channels = <2>;
926 clock-names = "adc";
927 fsl,adck-max-frequency = <30000000>, <40000000>,
933 #address-cells = <1>;
934 #size-cells = <0>;
935 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
943 #address-cells = <1>;
944 #size-cells = <0>;
945 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
953 #address-cells = <1>;
954 #size-cells = <0>;
955 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
962 memory-controller@21b0000 {
963 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
969 #address-cells = <2>;
970 #size-cells = <1>;
971 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
975 fsl,weim-cs-gpr = <&gpr>;
980 #address-cells = <1>;
981 #size-cells = <1>;
982 compatible = "fsl,imx6ul-ocotp", "syscon";
990 tempmon_temp_grade: temp-grade@20 {
994 cpu_speed_grade: speed-grade@10 {
1000 compatible = "fsl,imx6ul-csi";
1004 clock-names = "mclk";
1009 compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";
1015 clock-names = "pix", "axi", "disp_axi";
1020 compatible = "fsl,imx6ul-pxp";
1024 clock-names = "axi";
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030 compatible = "fsl,imx6ul-qspi";
1032 reg-names = "QuadSPI", "QuadSPI-memory";
1036 clock-names = "qspi_en", "qspi";
1041 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
1049 compatible = "fsl,imx6ul-uart",
1050 "fsl,imx6q-uart";
1055 clock-names = "ipg", "per";
1060 compatible = "fsl,imx6ul-uart",
1061 "fsl,imx6q-uart";
1066 clock-names = "ipg", "per";
1071 compatible = "fsl,imx6ul-uart",
1072 "fsl,imx6q-uart";
1077 clock-names = "ipg", "per";
1082 compatible = "fsl,imx6ul-uart",
1083 "fsl,imx6q-uart";
1088 clock-names = "ipg", "per";
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1095 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1103 compatible = "fsl,imx6ul-uart",
1104 "fsl,imx6q-uart";
1109 clock-names = "ipg", "per";