Lines Matching +full:gcc +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
27 no-map;
32 no-map;
44 #address-cells = <1>;
45 #size-cells = <0>;
48 compatible = "arm,cortex-a7";
49 enable-method = "qcom,kpss-acc-v2";
50 next-level-cache = <&L2>;
54 clocks = <&gcc GCC_APPS_CLK_SRC>;
55 clock-frequency = <0>;
56 clock-latency = <256000>;
57 operating-points-v2 = <&cpu0_opp_table>;
62 compatible = "arm,cortex-a7";
63 enable-method = "qcom,kpss-acc-v2";
64 next-level-cache = <&L2>;
68 clocks = <&gcc GCC_APPS_CLK_SRC>;
69 clock-frequency = <0>;
70 clock-latency = <256000>;
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "arm,cortex-a7";
77 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
83 clock-frequency = <0>;
84 clock-latency = <256000>;
85 operating-points-v2 = <&cpu0_opp_table>;
90 compatible = "arm,cortex-a7";
91 enable-method = "qcom,kpss-acc-v2";
92 next-level-cache = <&L2>;
96 clocks = <&gcc GCC_APPS_CLK_SRC>;
97 clock-frequency = <0>;
98 clock-latency = <256000>;
99 operating-points-v2 = <&cpu0_opp_table>;
102 L2: l2-cache {
104 cache-level = <2>;
110 compatible = "operating-points-v2";
111 opp-shared;
113 opp-48000000 {
114 opp-hz = /bits/ 64 <48000000>;
115 clock-latency-ns = <256000>;
117 opp-200000000 {
118 opp-hz = /bits/ 64 <200000000>;
119 clock-latency-ns = <256000>;
121 opp-500000000 {
122 opp-hz = /bits/ 64 <500000000>;
123 clock-latency-ns = <256000>;
125 opp-716000000 {
126 opp-hz = /bits/ 64 <716000000>;
127 clock-latency-ns = <256000>;
137 compatible = "arm,cortex-a7-pmu";
144 compatible = "fixed-clock";
145 clock-frequency = <32000>;
146 clock-output-names = "gcc_sleep_clk_src";
147 #clock-cells = <0>;
151 compatible = "fixed-clock";
152 clock-frequency = <48000000>;
153 #clock-cells = <0>;
159 compatible = "qcom,scm-ipq4019";
164 compatible = "arm,armv7-timer";
169 clock-frequency = <48000000>;
170 always-on;
174 #address-cells = <1>;
175 #size-cells = <1>;
177 compatible = "simple-bus";
179 intc: interrupt-controller@b000000 {
180 compatible = "qcom,msm-qgic2";
181 interrupt-controller;
182 #interrupt-cells = <3>;
187 gcc: clock-controller@1800000 { label
188 compatible = "qcom,gcc-ipq4019";
189 #clock-cells = <1>;
190 #reset-cells = <1>;
197 clocks = <&gcc GCC_PRNG_AHB_CLK>;
198 clock-names = "core";
203 compatible = "qcom,ipq4019-pinctrl";
205 gpio-controller;
206 gpio-ranges = <&tlmm 0 0 100>;
207 #gpio-cells = <2>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
214 compatible = "qcom,sdhci-msm-v4";
217 interrupt-names = "hc_irq", "pwr_irq";
218 bus-width = <8>;
219 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
220 <&gcc GCC_DCD_XO_CLK>;
221 clock-names = "core", "iface", "xo";
226 compatible = "qcom,bam-v1.7.0";
229 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
230 clock-names = "bam_clk";
231 #dma-cells = <1>;
237 compatible = "qcom,spi-qup-v2.2.1";
240 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
241 <&gcc GCC_BLSP1_AHB_CLK>;
242 clock-names = "core", "iface";
243 #address-cells = <1>;
244 #size-cells = <0>;
246 dma-names = "rx", "tx";
251 compatible = "qcom,spi-qup-v2.2.1";
254 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
255 <&gcc GCC_BLSP1_AHB_CLK>;
256 clock-names = "core", "iface";
257 #address-cells = <1>;
258 #size-cells = <0>;
260 dma-names = "rx", "tx";
265 compatible = "qcom,i2c-qup-v2.2.1";
268 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
269 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
270 clock-names = "iface", "core";
271 #address-cells = <1>;
272 #size-cells = <0>;
274 dma-names = "rx", "tx";
279 compatible = "qcom,i2c-qup-v2.2.1";
282 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
283 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
284 clock-names = "iface", "core";
285 #address-cells = <1>;
286 #size-cells = <0>;
288 dma-names = "rx", "tx";
293 compatible = "qcom,bam-v1.7.0";
296 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
297 clock-names = "bam_clk";
298 #dma-cells = <1>;
300 qcom,controlled-remotely;
305 compatible = "qcom,crypto-v5.1";
307 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
308 <&gcc GCC_CRYPTO_AXI_CLK>,
309 <&gcc GCC_CRYPTO_CLK>;
310 clock-names = "iface", "bus", "core";
312 dma-names = "rx", "tx";
316 acc0: clock-controller@b088000 {
317 compatible = "qcom,kpss-acc-v2";
321 acc1: clock-controller@b098000 {
322 compatible = "qcom,kpss-acc-v2";
326 acc2: clock-controller@b0a8000 {
327 compatible = "qcom,kpss-acc-v2";
331 acc3: clock-controller@b0b8000 {
332 compatible = "qcom,kpss-acc-v2";
367 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
371 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
372 <&gcc GCC_BLSP1_AHB_CLK>;
373 clock-names = "core", "iface";
375 dma-names = "rx", "tx";
379 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
383 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
384 <&gcc GCC_BLSP1_AHB_CLK>;
385 clock-names = "core", "iface";
387 dma-names = "rx", "tx";
391 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
394 timeout-sec = <10>;
404 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
409 reg-names = "dbi", "elbi", "parf", "config";
411 linux,pci-domain = <0>;
412 bus-range = <0x00 0xff>;
413 num-lanes = <1>;
414 #address-cells = <3>;
415 #size-cells = <2>;
421 interrupt-names = "msi";
422 #interrupt-cells = <1>;
423 interrupt-map-mask = <0 0 0 0x7>;
424 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
428 clocks = <&gcc GCC_PCIE_AHB_CLK>,
429 <&gcc GCC_PCIE_AXI_M_CLK>,
430 <&gcc GCC_PCIE_AXI_S_CLK>;
431 clock-names = "aux",
435 resets = <&gcc PCIE_AXI_M_ARES>,
436 <&gcc PCIE_AXI_S_ARES>,
437 <&gcc PCIE_PIPE_ARES>,
438 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
439 <&gcc PCIE_AXI_S_XPU_ARES>,
440 <&gcc PCIE_PARF_XPU_ARES>,
441 <&gcc PCIE_PHY_ARES>,
442 <&gcc PCIE_AXI_M_STICKY_ARES>,
443 <&gcc PCIE_PIPE_STICKY_ARES>,
444 <&gcc PCIE_PWR_ARES>,
445 <&gcc PCIE_AHB_ARES>,
446 <&gcc PCIE_PHY_AHB_ARES>;
447 reset-names = "axi_m",
464 compatible = "qcom,bam-v1.7.0";
467 clocks = <&gcc GCC_QPIC_CLK>;
468 clock-names = "bam_clk";
469 #dma-cells = <1>;
474 nand: qpic-nand@79b0000 {
475 compatible = "qcom,ipq4019-nand";
477 #address-cells = <1>;
478 #size-cells = <0>;
479 clocks = <&gcc GCC_QPIC_CLK>,
480 <&gcc GCC_QPIC_AHB_CLK>;
481 clock-names = "core", "aon";
486 dma-names = "tx", "rx", "cmd";
492 nand-ecc-strength = <4>;
493 nand-ecc-step-size = <512>;
494 nand-bus-width = <8>;
499 compatible = "qcom,ipq4019-wifi";
501 resets = <&gcc WIFI0_CPU_INIT_RESET>,
502 <&gcc WIFI0_RADIO_SRIF_RESET>,
503 <&gcc WIFI0_RADIO_WARM_RESET>,
504 <&gcc WIFI0_RADIO_COLD_RESET>,
505 <&gcc WIFI0_CORE_WARM_RESET>,
506 <&gcc WIFI0_CORE_COLD_RESET>;
507 reset-names = "wifi_cpu_init", "wifi_radio_srif",
510 clocks = <&gcc GCC_WCSS2G_CLK>,
511 <&gcc GCC_WCSS2G_REF_CLK>,
512 <&gcc GCC_WCSS2G_RTC_CLK>;
513 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
532 interrupt-names = "msi0", "msi1", "msi2", "msi3",
541 compatible = "qcom,ipq4019-wifi";
543 resets = <&gcc WIFI1_CPU_INIT_RESET>,
544 <&gcc WIFI1_RADIO_SRIF_RESET>,
545 <&gcc WIFI1_RADIO_WARM_RESET>,
546 <&gcc WIFI1_RADIO_COLD_RESET>,
547 <&gcc WIFI1_CORE_WARM_RESET>,
548 <&gcc WIFI1_CORE_COLD_RESET>;
549 reset-names = "wifi_cpu_init", "wifi_radio_srif",
552 clocks = <&gcc GCC_WCSS5G_CLK>,
553 <&gcc GCC_WCSS5G_REF_CLK>,
554 <&gcc GCC_WCSS5G_RTC_CLK>;
555 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
574 interrupt-names = "msi0", "msi1", "msi2", "msi3",
583 #address-cells = <1>;
584 #size-cells = <0>;
585 compatible = "qcom,ipq4019-mdio";
589 ethphy0: ethernet-phy@0 {
593 ethphy1: ethernet-phy@1 {
597 ethphy2: ethernet-phy@2 {
601 ethphy3: ethernet-phy@3 {
605 ethphy4: ethernet-phy@4 {