Lines Matching +full:kpss +full:- +full:gcc
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/mfd/qcom-rpm.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <0>;
23 enable-method = "qcom,kpss-acc-v1";
26 next-level-cache = <&L2>;
33 enable-method = "qcom,kpss-acc-v1";
36 next-level-cache = <&L2>;
41 L2: l2-cache {
43 cache-level = <2>;
52 cpu-pmu {
53 compatible = "qcom,krait-pmu";
55 qcom,no-pc-write;
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <19200000>;
63 clock-output-names = "cxo_board";
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <27000000>;
70 clock-output-names = "pxo_board";
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <32768>;
77 clock-output-names = "sleep_clk";
82 #address-cells = <1>;
83 #size-cells = <1>;
85 compatible = "simple-bus";
87 intc: interrupt-controller@2000000 {
88 compatible = "qcom,msm-qgic2";
89 interrupt-controller;
90 #interrupt-cells = <3>;
96 compatible = "qcom,kpss-timer",
97 "qcom,kpss-wdt-msm8960", "qcom,msm-timer";
102 clock-frequency = <27000000>,
104 cpu-offset = <0x80000>;
108 compatible = "qcom,msm8960-pinctrl";
109 gpio-controller;
110 gpio-ranges = <&msmgpio 0 0 152>;
111 #gpio-cells = <2>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
118 gcc: clock-controller@900000 { label
119 compatible = "qcom,gcc-msm8960";
120 #clock-cells = <1>;
121 #reset-cells = <1>;
125 lcc: clock-controller@28000000 {
126 compatible = "qcom,lcc-msm8960";
128 #clock-cells = <1>;
129 #reset-cells = <1>;
132 clock-controller@4000000 {
133 compatible = "qcom,mmcc-msm8960";
135 #clock-cells = <1>;
136 #reset-cells = <1>;
139 l2cc: clock-controller@2011000 {
145 compatible = "qcom,rpm-msm8960";
152 interrupt-names = "ack", "err", "wakeup";
155 compatible = "qcom,rpm-pm8921-regulators";
159 acc0: clock-controller@2088000 {
160 compatible = "qcom,kpss-acc-v1";
164 acc1: clock-controller@2098000 {
165 compatible = "qcom,kpss-acc-v1";
182 compatible = "qcom,gsbi-v1.0.0";
183 cell-index = <5>;
185 clocks = <&gcc GSBI5_H_CLK>;
186 clock-names = "iface";
187 #address-cells = <1>;
188 #size-cells = <1>;
191 syscon-tcsr = <&tcsr>;
194 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
198 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
199 clock-names = "core", "iface";
207 qcom,controller-type = "pmic-arbiter";
211 interrupt-parent = <&msmgpio>;
213 #interrupt-cells = <2>;
214 interrupt-controller;
215 #address-cells = <1>;
216 #size-cells = <0>;
219 compatible = "qcom,pm8921-pwrkey";
221 interrupt-parent = <&pmicintc>;
224 pull-up;
228 compatible = "qcom,pm8921-keypad";
230 interrupt-parent = <&pmicintc>;
233 scan-delay = <32>;
234 row-hold = <91500>;
238 compatible = "qcom,pm8921-rtc";
239 interrupt-parent = <&pmicintc>;
242 allow-set-time;
250 clocks = <&gcc PRNG_CLK>;
251 clock-names = "core";
255 vsdcc_fixed: vsdcc-regulator {
256 compatible = "regulator-fixed";
257 regulator-name = "SDCC Power";
258 regulator-min-microvolt = <2700000>;
259 regulator-max-microvolt = <2700000>;
260 regulator-always-on;
264 compatible = "simple-bus";
265 #address-cells = <1>;
266 #size-cells = <1>;
271 arm,primecell-periphid = <0x00051180>;
274 interrupt-names = "cmd_irq";
275 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
276 clock-names = "mclk", "apb_pclk";
277 bus-width = <8>;
278 max-frequency = <96000000>;
279 non-removable;
280 cap-sd-highspeed;
281 cap-mmc-highspeed;
282 vmmc-supply = <&vsdcc_fixed>;
287 arm,primecell-periphid = <0x00051180>;
291 interrupt-names = "cmd_irq";
292 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
293 clock-names = "mclk", "apb_pclk";
294 bus-width = <4>;
295 cap-sd-highspeed;
296 cap-mmc-highspeed;
297 max-frequency = <192000000>;
298 no-1-8-v;
299 vmmc-supply = <&vsdcc_fixed>;
304 compatible = "qcom,tcsr-msm8960", "syscon";
309 compatible = "qcom,gsbi-v1.0.0";
310 cell-index = <1>;
312 clocks = <&gcc GSBI1_H_CLK>;
313 clock-names = "iface";
314 #address-cells = <1>;
315 #size-cells = <1>;
319 compatible = "qcom,spi-qup-v1.1.1";
320 #address-cells = <1>;
321 #size-cells = <0>;
324 spi-max-frequency = <24000000>;
325 cs-gpios = <&msmgpio 8 0>;
327 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
328 clock-names = "core", "iface";