29 			0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);  in ksz9021rn_phy_fixup()
30 		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);  in ksz9021rn_phy_fixup()
34 			0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);  in ksz9021rn_phy_fixup()
35 		phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);  in ksz9021rn_phy_fixup()
40 	return 0;  in ksz9021rn_phy_fixup()
45 	phy_write(dev, 0x0d, device);  in mmd_write_reg()
46 	phy_write(dev, 0x0e, reg);  in mmd_write_reg()
47 	phy_write(dev, 0x0d, (1 << 14) | device);  in mmd_write_reg()
48 	phy_write(dev, 0x0e, val);  in mmd_write_reg()
57 	mmd_write_reg(dev, 2, 4, 0);  in ksz9031rn_phy_fixup()
58 	mmd_write_reg(dev, 2, 5, 0);  in ksz9031rn_phy_fixup()
59 	mmd_write_reg(dev, 2, 8, 0x003ff);  in ksz9031rn_phy_fixup()
61 	return 0;  in ksz9031rn_phy_fixup()
75 	if (dev->devfn != 0)  in ventana_pciesw_early_fixup()
78 	pci_read_config_dword(dev, 0x62c, &dw);  in ventana_pciesw_early_fixup()
79 	dw |= 0xaaa8; // GPIO1-7 outputs  in ventana_pciesw_early_fixup()
80 	pci_write_config_dword(dev, 0x62c, dw);  in ventana_pciesw_early_fixup()
82 	pci_read_config_dword(dev, 0x644, &dw);  in ventana_pciesw_early_fixup()
83 	dw |= 0xfe;   // GPIO1-7 output high  in ventana_pciesw_early_fixup()
84 	pci_write_config_dword(dev, 0x644, dw);  in ventana_pciesw_early_fixup()
88 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
89 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
90 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
97 	phy_write(dev, 0xd, 0x7);  in ar8031_phy_fixup()
98 	phy_write(dev, 0xe, 0x8016);  in ar8031_phy_fixup()
99 	phy_write(dev, 0xd, 0x4007);  in ar8031_phy_fixup()
101 	val = phy_read(dev, 0xe);  in ar8031_phy_fixup()
102 	val &= 0xffe3;  in ar8031_phy_fixup()
103 	val |= 0x18;  in ar8031_phy_fixup()
104 	phy_write(dev, 0xe, val);  in ar8031_phy_fixup()
107 	phy_write(dev, 0x1d, 0x5);  in ar8031_phy_fixup()
108 	val = phy_read(dev, 0x1e);  in ar8031_phy_fixup()
109 	val |= 0x0100;  in ar8031_phy_fixup()
110 	phy_write(dev, 0x1e, val);  in ar8031_phy_fixup()
112 	return 0;  in ar8031_phy_fixup()
115 #define PHY_ID_AR8031	0x004dd074
124 	phy_write(dev, 0xd, 0x3);  in ar8035_phy_fixup()
125 	phy_write(dev, 0xe, 0x805d);  in ar8035_phy_fixup()
126 	phy_write(dev, 0xd, 0x4003);  in ar8035_phy_fixup()
128 	val = phy_read(dev, 0xe);  in ar8035_phy_fixup()
129 	phy_write(dev, 0xe, val & ~(1 << 8));  in ar8035_phy_fixup()
141 	val = phy_read(dev, 0x0);  in ar8035_phy_fixup()
143 		phy_write(dev, 0x0, val & ~BMCR_PDOWN);  in ar8035_phy_fixup()
145 	return 0;  in ar8035_phy_fixup()
148 #define PHY_ID_AR8035 0x004dd072
157 		phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef,  in imx6q_enet_phy_init()
159 		phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,  in imx6q_enet_phy_init()
236 				(0xf << 16) | (0x7 << 20));  in imx6q_axi_init()
240 				(0xf << 16) | (0x7 << 20));  in imx6q_axi_init()
277 		platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);  in imx6q_init_late()
304 	.l2c_aux_val 	= 0,
305 	.l2c_aux_mask	= ~0,