Lines Matching +full:anatop +full:- +full:enable +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
65 * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
66 * as they are used for slots1-7 PERST#
75 if (dev->devfn != 0) in ventana_pciesw_early_fixup()
79 dw |= 0xaaa8; // GPIO1-7 outputs in ventana_pciesw_early_fixup()
83 dw |= 0xfe; // GPIO1-7 output high in ventana_pciesw_early_fixup()
96 /* To enable AR8031 output a 125MHz clk from CLK_25M */ in ar8031_phy_fixup()
132 * Enable 125MHz clock from CLK_25M on the AR8031. This in ar8035_phy_fixup()
172 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); in imx6q_1588_init()
191 * If enet_ref from ANATOP/CCM is the PTP clock source, we need to in imx6q_1588_init()
192 * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad in imx6q_1588_init()
193 * (external OSC), and we need to clear the bit. in imx6q_1588_init()
198 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); in imx6q_1588_init()
204 pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); in imx6q_1588_init()
218 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); in imx6q_axi_init()
221 * Enable the cacheable attribute of VPU and IPU in imx6q_axi_init()
242 pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); in imx6q_axi_init()
277 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); in imx6q_init_late()
293 imx6_pm_ccm_init("fsl,imx6q-ccm"); in imx6q_init_irq()