1 // SPDX-License-Identifier: GPL-2.0-only
6  *  Modifications for ARM processor (c) 1995-2001 Russell King
8  *  - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
33  * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
53 #define LDSTHD_I_BIT(i)	(i & (1 << 22))		/* double/half-word immed */
73 /* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
105 	 * LDM, STM, LDRD and STRD still need to be handled.  in safe_usermode()
108 	 * CPUs since we spin re-faulting the instruction without  in safe_usermode()
159 			return -EFAULT;  in alignment_proc_write()
161 			ai_usermode = safe_usermode(mode - '0', true);  in alignment_proc_write()
322 		offset.un = -offset.un;  in do_alignment_finish_ldst()
328 		regs->uregs[RN_BITS(instr)] = addr;  in do_alignment_finish_ldst()
345 		/* signed half-word? */  in do_alignment_ldrhstrh()
349 		regs->uregs[rd] = val;  in do_alignment_ldrhstrh()
351 		put16_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrhstrh()
363 		/* signed half-word? */  in do_alignment_ldrhstrh()
367 		regs->uregs[rd] = val;  in do_alignment_ldrhstrh()
370 		put16t_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrhstrh()
388 		/* ARMv7 Thumb-2 32-bit LDRD/STRD */  in do_alignment_ldrdstrd()
406 		regs->uregs[rd] = val;  in do_alignment_ldrdstrd()
408 		regs->uregs[rd2] = val;  in do_alignment_ldrdstrd()
410 		put32_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrdstrd()
411 		put32_unaligned_check(regs->uregs[rd2], addr + 4);  in do_alignment_ldrdstrd()
426 		regs->uregs[rd] = val;  in do_alignment_ldrdstrd()
427 		regs->uregs[rd2] = val2;  in do_alignment_ldrdstrd()
430 		put32t_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrdstrd()
431 		put32t_unaligned_check(regs->uregs[rd2], addr + 4);  in do_alignment_ldrdstrd()
455 		regs->uregs[rd] = val;  in do_alignment_ldrstr()
457 		put32_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrstr()
466 		regs->uregs[rd] = val;  in do_alignment_ldrstr()
469 		put32t_unaligned_check(regs->uregs[rd], addr);  in do_alignment_ldrstr()
479  * LDM/STM alignment handler.
484  *              ------ increasing address ----->
501 	regs->ARM_pc += correction;  in do_alignment_ldmstm()
509 	newaddr = eaddr = regs->uregs[rn];  in do_alignment_ldmstm()
512 		nr_regs = -nr_regs;  in do_alignment_ldmstm()
522 	 * the FSR (and hence addr) equal to the updated base address  in do_alignment_ldmstm()
529 	 * This is a "hint" - we already have eaddr worked out by the  in do_alignment_ldmstm()
548 					regs->uregs[rd] = val;  in do_alignment_ldmstm()
550 					put32t_unaligned_check(regs->uregs[rd], eaddr);  in do_alignment_ldmstm()
561 					regs->uregs[rd] = val;  in do_alignment_ldmstm()
563 					put32_unaligned_check(regs->uregs[rd], eaddr);  in do_alignment_ldmstm()
569 		regs->uregs[rn] = newaddr;  in do_alignment_ldmstm()
571 		regs->ARM_pc -= correction;  in do_alignment_ldmstm()
575 	regs->ARM_pc -= correction;  in do_alignment_ldmstm()
579 	pr_err("Alignment trap: not handling ldm with s-bit set\n");  in do_alignment_ldmstm()
593  * 2. If for some reason we're passed an non-ld/st Thumb instruction to
611 			((tinstr & (1<<12)) << (22-12)) |	/* fixup */  in thumb2arm()
613 			((tinstr & (7<<0)) << (12-0)) |		/* Rd */  in thumb2arm()
614 			((tinstr & (7<<3)) << (16-3)) |		/* Rn */  in thumb2arm()
616 				(6 - ((tinstr & (1<<12)) ? 0 : 2)));  in thumb2arm()
621 			((tinstr & (7<<0)) << (12-0)) |		/* Rd */  in thumb2arm()
622 			((tinstr & (7<<3)) << (16-3)) |		/* Rn */  in thumb2arm()
623 			((tinstr & (7<<6)) >> (6-1)) |	 /* immed_5[2:0] */  in thumb2arm()
624 			((tinstr & (3<<9)) >> (9-8));	 /* immed_5[4:3] */  in thumb2arm()
641 			    ((tinstr & (7<<0)) << (12-0)) |	/* Rd */  in thumb2arm()
642 			    ((tinstr & (7<<3)) << (16-3)) |	/* Rn */  in thumb2arm()
643 			    ((tinstr & (7<<6)) >> (6-0));	/* Rm */  in thumb2arm()
649 		 *	 loading 32-bit memory data via PC relative  in thumb2arm()
654 		    ((tinstr & (7<<8)) << (12-8)) |		/* Rd */  in thumb2arm()
655 		    ((tinstr & 255) << (2-0));			/* immed_8 */  in thumb2arm()
662 			((tinstr & (7<<8)) << (12-8)) |		/* Rd */  in thumb2arm()
697  * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
701  * @pinstr: original Thumb-2 instruction; returns new handlable instruction
719 	case 0xe880:		/* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */  in do_alignment_t32_to_handler()
744 		poffset->un = (tinst2 & 0xff) << 2;  in do_alignment_t32_to_handler()
816 				/* Thumb-2 32-bit */  in do_alignment()
843 	regs->ARM_pc += isize;  in do_alignment()
850 			offset.un = regs->uregs[RM_BITS(instr)];  in do_alignment()
872 		offset.un = regs->uregs[RM_BITS(instr)];  in do_alignment()
893 					if (regs->ARM_cpsr & PSR_C_BIT)  in do_alignment()
897 							  offset.un << (32 - shiftval);  in do_alignment()
904 	case 0x08000000:	/* ldm or stm, or thumb-2 32bit instruction */  in do_alignment()
923 		regs->ARM_pc -= isize;  in do_alignment()
931 		regs->ARM_cpsr = it_advance(regs->ARM_cpsr);  in do_alignment()
939 	 * We got a fault - fix it up, or die.  in do_alignment()
963 		       "Address=0x%08lx FSR 0x%03x\n", current->comm,  in do_alignment()
980 		 * the alignment trap won't be re-enabled in that case as it  in do_alignment()
984 		 * entry-common.S) and disable the alignment trap only if  in do_alignment()
988 		if (!(current_thread_info()->flags & _TIF_WORK_MASK))  in do_alignment()
1016 		return -ENOMEM;  in alignment_init()