Lines Matching +full:1 +full:c0
22 #define TTB_C (1 << 0)
23 #define TTB_S (1 << 1)
24 #define TTB_IMP (1 << 2)
26 #define TTB_RGN_WBWA (1 << 3)
39 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
76 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
80 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
83 bhi 1b
104 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
106 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
111 mcr p15, 0, r1, c13, c0, 1 @ set context ID
139 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
141 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
142 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
144 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
145 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
146 mrc p15, 0, r9, c1, c0, 0 @ control register
157 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
159 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
161 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
164 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
165 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
166 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
168 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
169 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
197 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
200 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
210 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
215 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
221 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
222 mrc p15, 0, r0, c1, c0, 0 @ read control register
234 mrc p15, 0, r5, c0, c0, 0 @ get processor id
236 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
237 orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
238 mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
239 orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
256 define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1