Lines Matching +full:disable +full:- +full:mmu +full:- +full:reset

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  linux/arch/arm/mm/proc-v6.S
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
18 #include "proc-macros.S"
42 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
48  *	Perform a soft reset of the system.  Put the CPU into the
49  *	same state as it would be if it had been reset, and branch
50  *	to what would be the reset vector.
52  *	- loc   - location to jump to for soft reset
59 	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
75 	mcr	p15, 0, r1, c7, c10, 4		@ DWB - WFI may enter a low-power mode
91  *	- pgd_phys - physical address of new TTB
94  *	- we are not using split page tables
99 	mmid	r1, r1				@ get mm->context.id
120  *	- ptep  - pointer to level 2 translation table entry
121  *		  (hardware version is stored at -1024 bytes)
122  *	- pte   - PTE value to store
123  *	- ext	- value for extended PTE bits
133 /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
138 	stmfd	sp!, {r4 - r9, lr}
145 	mrc	p15, 0, r8, c1, c0, 2	@ co-processor access control
147 	stmia	r0, {r4 - r9}
148 	ldmfd	sp!, {r4- r9, pc}
158 	ldmia	r0, {r4 - r9}
169 	mcr	p15, 0, r8, c1, c0, 2	@ co-processor access control
176 	string	cpu_v6_name, "ARMv6-compatible processor"
183  *	Initialise TLB, Caches, and MMU state ready to switch the MMU
193  *	- cache type register is implemented
221  ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
228 	 * corruption with hit-under-miss enabled). The conditional code below
230 	 * and the FI bit in the control register) disables hit-under-miss
255 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
297 	.size	__v6_proc_info, . - __v6_proc_info