Lines Matching +full:1 +full:c0
32 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
57 THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
83 ALT_UP_B(1f)
85 1: dcache_line_size r2, r3
86 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
134 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
135 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
138 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
140 mrrc p15, 1, r5, r7, c2 @ TTB 1
142 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
144 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
146 mrc p15, 0, r8, c1, c0, 0 @ Control register
147 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
148 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
156 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
158 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
159 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
163 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
166 mcrr p15, 1, r5, r7, c2 @ TTB 1
170 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
171 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
173 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
177 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
179 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
181 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
182 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
195 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
196 mrc p15, 0, r5, c15, c0, 0 @ Power register
204 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
206 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
207 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
209 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
234 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
235 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
236 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
237 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
246 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
247 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
248 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
249 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
280 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
281 b 1f
288 1: adr r0, __v7_setup_stack_ptr
295 orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode
296 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
300 mcrne p15, 0, r10, c1, c0, 1 @ No, update register
315 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
316 orreq r0, r0, #(1 << 6) @ set IBE to 1
317 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
321 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
322 orreq r0, r0, #(1 << 5) @ set L1NEON to 1
323 orreq r0, r0, #(1 << 9) @ set PLDNOP to 1
324 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
328 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
329 tsteq r0, #1 << 22
330 orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit
331 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
338 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
339 orrle r0, r0, #1 << 4 @ set bit #4
340 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
346 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
347 orreq r0, r0, #1 << 12 @ set bit #12
348 orreq r0, r0, #1 << 22 @ set bit #22
349 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
353 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
354 orreq r0, r0, #1 << 6 @ set bit #6
355 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
359 ALT_UP_B(1f)
360 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
361 orrlt r0, r0, #1 << 11 @ set bit #11
362 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
363 1:
370 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
371 orrle r0, r0, #1 << 1 @ disable loop buffer
372 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
378 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
379 orr r10, r10, #1 << 12 @ set bit #12
380 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
383 mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg
384 orr r10, r10, #1 << 1 @ set bit #1
385 mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg
388 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
389 orr r10, r10, #1 << 24 @ set bit #24
390 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
393 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
395 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
402 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
403 orrle r10, r10, #1 << 24 @ set bit #24
404 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
408 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
409 orrle r10, r10, #1 << 12 @ set bit #12
410 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
413 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
415 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
422 /* Auxiliary Debug Modes Control 1 Register */
423 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
424 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
425 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
428 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
429 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
430 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
431 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
432 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
437 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
438 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
439 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
442 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
444 /* Auxiliary Debug Modes Control 1 Register */
445 mrc p15, 1, r0, c15, c1, 1
449 mcr p15, 1, r0, c15, c1, 1
452 mrc p15, 1, r0, c15, c1, 2
455 mcr p15, 1, r0, c15, c1, 2
458 mrc p15, 1, r0, c15, c2, 0
464 mcr p15, 1, r0, c15, c2, 0
467 mrc p15, 1, r0, c15, c1, 0
469 mcr p15, 1, r0, c15, c1, 0
524 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
528 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
530 teq r0, #(1 << 12) @ check if ThumbEE is present
531 bne 1f
533 mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0
534 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
535 orr r0, r0, #1 @ set the 1st bit in order to
536 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
537 1:
541 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
543 orr r3, r3, #(1 << 10) @ set SW bit in "clear"
544 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
546 mrc p15, 0, r0, c1, c0, 0 @ read control register
549 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
567 …define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bug…
582 …define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu…
603 …define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca…
618 …define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_…
636 …define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_c…
638 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1