Lines Matching +full:2 +full:c0
24 #include "proc-v7-2level.S"
32 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
58 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
86 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
89 bhi 2b
134 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
135 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
138 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
142 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
144 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
146 mrc p15, 0, r8, c1, c0, 0 @ Control register
147 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
148 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
156 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
158 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
159 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
163 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
170 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
171 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
173 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
179 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
181 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
182 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
191 .equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
195 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
196 mrc p15, 0, r5, c15, c0, 0 @ Power register
204 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
206 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
207 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
209 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
236 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
248 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
296 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
300 mcrne p15, 0, r10, c1, c0, 1 @ No, update register
315 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
317 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
321 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
324 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
328 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
331 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
338 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
340 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
346 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
349 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
353 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
355 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
360 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
362 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
370 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
372 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
378 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
380 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
383 mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg
385 mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg
388 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
390 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
393 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
395 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
402 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
404 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
408 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
410 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
413 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
415 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
423 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
427 /* Auxiliary Debug Modes Control 2 Register */
438 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
451 /* Auxiliary Debug Modes Control 2 Register */
452 mrc p15, 1, r0, c15, c1, 2
455 mcr p15, 1, r0, c15, c1, 2
528 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
533 mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0
534 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
536 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
546 mrc p15, 0, r0, c1, c0, 0 @ read control register
552 .align 2
558 .align 2