Lines Matching +full:parent +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
27 struct clk clkin1 = {
39 .parent = &clkin1,
45 .parent = &c6x_soc_pll1.sysclks[0],
50 .parent = &c6x_soc_pll1.sysclks[0],
55 .parent = &c6x_soc_pll1.sysclks[0],
60 .parent = &c6x_soc_pll1.sysclks[0],
65 .parent = &c6x_soc_pll1.sysclks[0],
70 .parent = &c6x_soc_pll1.sysclks[0],
75 .parent = &c6x_soc_pll1.sysclks[0],
80 .parent = &c6x_soc_pll1.sysclks[0],
85 .parent = &c6x_soc_pll1.sysclks[0],
90 .parent = &c6x_soc_pll1.sysclks[0],
95 .parent = &c6x_soc_pll1.sysclks[0],
100 .parent = &c6x_soc_pll1.sysclks[0],
105 .parent = &c6x_soc_pll1.sysclks[0],
110 .parent = &c6x_soc_pll1.sysclks[0],
115 .parent = &c6x_soc_pll1.sysclks[0],
120 .parent = &c6x_soc_pll1.sysclks[0],
127 struct clk c6x_core_clk = {
132 struct clk c6x_i2c_clk = {
136 struct clk c6x_watchdog_clk = {
140 struct clk c6x_mcbsp1_clk = {
144 struct clk c6x_mcbsp2_clk = {
148 struct clk c6x_mdio_clk = {
155 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
156 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
157 CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
158 CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
159 CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
160 CLK(NULL, "core", &c6x_core_clk),
161 CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
162 CLK("watchdog", NULL, &c6x_watchdog_clk),
163 CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
164 CLK("", NULL, NULL)
171 struct clk *sysclks = pll->sysclks; in c6455_setup_clocks()
173 pll->flags = PLL_HAS_PRE | PLL_HAS_MUL; in c6455_setup_clocks()
182 c6x_core_clk.parent = &sysclks[0]; in c6455_setup_clocks()
183 c6x_i2c_clk.parent = &sysclks[3]; in c6455_setup_clocks()
184 c6x_watchdog_clk.parent = &sysclks[3]; in c6455_setup_clocks()
185 c6x_mdio_clk.parent = &sysclks[3]; in c6455_setup_clocks()
193 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
194 CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
195 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
196 CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
197 CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
198 CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
199 CLK(NULL, "core", &c6x_core_clk),
200 CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
201 CLK("watchdog", NULL, &c6x_watchdog_clk),
202 CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
203 CLK("", NULL, NULL)
209 struct clk *sysclks = pll->sysclks; in c6457_setup_clocks()
211 pll->flags = PLL_HAS_MUL | PLL_HAS_POST; in c6457_setup_clocks()
222 c6x_core_clk.parent = &sysclks[1]; in c6457_setup_clocks()
223 c6x_i2c_clk.parent = &sysclks[3]; in c6457_setup_clocks()
224 c6x_watchdog_clk.parent = &sysclks[5]; in c6457_setup_clocks()
225 c6x_mdio_clk.parent = &sysclks[5]; in c6457_setup_clocks()
233 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
234 CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
235 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
236 CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
237 CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
238 CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
239 CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
240 CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
241 CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
242 CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
243 CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
244 CLK(NULL, "core", &c6x_core_clk),
245 CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
246 CLK("watchdog", NULL, &c6x_watchdog_clk),
247 CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
248 CLK("", NULL, NULL)
259 struct clk *sysclks = pll->sysclks; in c6472_setup_clocks()
262 pll->flags = PLL_HAS_MUL; in c6472_setup_clocks()
277 c6x_core_clk.parent = &sysclks[get_coreid() + 1]; in c6472_setup_clocks()
278 c6x_i2c_clk.parent = &sysclks[8]; in c6472_setup_clocks()
279 c6x_watchdog_clk.parent = &sysclks[8]; in c6472_setup_clocks()
280 c6x_mdio_clk.parent = &sysclks[5]; in c6472_setup_clocks()
289 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
290 CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
291 CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
292 CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
293 CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
294 CLK(NULL, "pll1_sysclk12", &c6x_soc_pll1.sysclks[12]),
295 CLK(NULL, "pll1_sysclk13", &c6x_soc_pll1.sysclks[13]),
296 CLK(NULL, "core", &c6x_core_clk),
297 CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
298 CLK("mcbsp.1", NULL, &c6x_mcbsp1_clk),
299 CLK("mcbsp.2", NULL, &c6x_mcbsp2_clk),
300 CLK("watchdog", NULL, &c6x_watchdog_clk),
301 CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
302 CLK("", NULL, NULL)
308 struct clk *sysclks = pll->sysclks; in c6474_setup_clocks()
310 pll->flags = PLL_HAS_MUL; in c6474_setup_clocks()
326 c6x_core_clk.parent = &sysclks[7]; in c6474_setup_clocks()
327 c6x_i2c_clk.parent = &sysclks[10]; in c6474_setup_clocks()
328 c6x_watchdog_clk.parent = &sysclks[10]; in c6474_setup_clocks()
329 c6x_mcbsp1_clk.parent = &sysclks[10]; in c6474_setup_clocks()
330 c6x_mcbsp2_clk.parent = &sysclks[10]; in c6474_setup_clocks()
338 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
339 CLK(NULL, "pll1_refclk", &c6x_soc_pll1.sysclks[1]),
340 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
341 CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
342 CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
343 CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
344 CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
345 CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
346 CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
347 CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
348 CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
349 CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
350 CLK(NULL, "core", &c6x_core_clk),
351 CLK("", NULL, NULL)
357 struct clk *sysclks = pll->sysclks; in c6678_setup_clocks()
359 pll->flags = PLL_HAS_MUL; in c6678_setup_clocks()
391 c6x_core_clk.parent = &sysclks[0]; in c6678_setup_clocks()
392 c6x_i2c_clk.parent = &sysclks[7]; in c6678_setup_clocks()
400 { .compatible = "ti,c6455-pll", .data = c6455_setup_clocks },
403 { .compatible = "ti,c6457-pll", .data = c6457_setup_clocks },
406 { .compatible = "ti,c6472-pll", .data = c6472_setup_clocks },
409 { .compatible = "ti,c6474-pll", .data = c6474_setup_clocks },
412 { .compatible = "ti,c6678-pll", .data = c6678_setup_clocks },
431 pll->base = of_iomap(node, 0); in c64x_setup_clocks()
432 if (!pll->base) in c64x_setup_clocks()
435 err = of_property_read_u32(node, "clock-frequency", &val); in c64x_setup_clocks()
437 pr_err("%pOF: no clock-frequency found! Using %dMHz\n", in c64x_setup_clocks()
443 err = of_property_read_u32(node, "ti,c64x+pll-bypass-delay", &val); in c64x_setup_clocks()
446 pll->bypass_delay = val; in c64x_setup_clocks()
448 err = of_property_read_u32(node, "ti,c64x+pll-reset-delay", &val); in c64x_setup_clocks()
451 pll->reset_delay = val; in c64x_setup_clocks()
453 err = of_property_read_u32(node, "ti,c64x+pll-lock-delay", &val); in c64x_setup_clocks()
456 pll->lock_delay = val; in c64x_setup_clocks()
458 /* id->data is a pointer to SoC-specific setup */ in c64x_setup_clocks()
460 if (id && id->data) { in c64x_setup_clocks()
461 __setup_clocks = id->data; in c64x_setup_clocks()