Lines Matching +full:0 +full:x3a0
21 #define LS7A_ROUTE_ENTRY_OFFSET 0x100
22 #define LS7A_INT_ID_OFFSET 0x0
23 #define LS7A_INT_ID_VAL 0x7000000UL
24 #define LS7A_INT_ID_VER 0x1f0001UL
25 #define LS7A_INT_MASK_OFFSET 0x20
26 #define LS7A_INT_EDGE_OFFSET 0x60
27 #define LS7A_INT_CLEAR_OFFSET 0x80
28 #define LS7A_INT_STATUS_OFFSET 0x3a0
29 #define LS7A_INT_POL_OFFSET 0x3e0
30 #define LS7A_HTMSI_EN_OFFSET 0x40
31 #define LS7A_HTMSI_VEC_OFFSET 0x200
32 #define LS7A_AUTO_CTRL0_OFFSET 0xc0
33 #define LS7A_AUTO_CTRL1_OFFSET 0xe0
35 #define LS7A_IOAPIC_GUEST_REG_BASE 0x10000000UL
36 #define LS7A_IOAPIC_GUEST_REG_BASE_ALIAS 0xe0010000000UL
42 /* 0x020 interrupt mask register */
44 /* 0x040 1=msi */
46 /* 0x060 edge=1 level =0 */
48 /* 0x080 for clean edge int,set 1 clean,set 0 is noused */
50 /* 0x0c0 */
52 /* 0x0e0 */
54 /* 0x100 - 0x140 */
56 /* 0x200 - 0x240 */
58 /* 0x300 */
60 /* 0x320 */
64 /* 0x380 interrupt request register */
66 /* 0x3a0 interrupt service register */
68 /* 0x3e0 interrupt level polarity selection register,
69 * 0 for high level tirgger