Lines Matching +full:supervisor +full:- +full:level
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
12 # include <asm-generic/mmu.h>
30 unsigned long w:1; /* Write-thru cache mode */
39 # define PP_RWXX 0 /* Supervisor read/write, User none */
40 # define PP_RWRX 1 /* Supervisor read/write, User read */
41 # define PP_RWRW 2 /* Supervisor read/write, User read/write */
42 # define PP_RXRX 3 /* Supervisor read, User read */
47 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
49 unsigned long n:1; /* No-execute */
58 * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB
65 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
66 * instruction and data sides share a unified, 64-entry, semi-associative
68 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
69 * TLB which serves as a first level to the shared TLB. These two TLBs are
83 * portion. The data portion is 32-bits.
116 # define TLB_W 0x00000008 /* Caching is write-through */