Lines Matching +full:0 +full:x40b
31 #define MAX_DMA_ADDRESS (~0UL)
44 * controller 1: channels 0-3, byte operations, ports 00-1F
49 * - channels 0-3 are byte - addresses/counts are for physical bytes
51 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
54 * - page registers for 5-7 don't use data bit 0, represent 128K pages
55 * - page registers for 0-3 use bit 0, represent 64K pages
61 * Address mapping for channels 0-3:
76 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
84 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
90 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
91 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
94 #define DMA1_CMD_REG 0x08 /* command register (w) */
95 #define DMA1_STAT_REG 0x08 /* status register (r) */
96 #define DMA1_REQ_REG 0x09 /* request register (w) */
97 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
98 #define DMA1_MODE_REG 0x0B /* mode register (w) */
99 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
100 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
101 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
102 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
103 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
105 #define DMA2_CMD_REG 0xD0 /* command register (w) */
106 #define DMA2_STAT_REG 0xD0 /* status register (r) */
107 #define DMA2_REQ_REG 0xD2 /* request register (w) */
108 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
109 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
110 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
111 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
112 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
113 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
114 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
116 #define DMA_ADDR_0 0x00 /* DMA address registers */
117 #define DMA_ADDR_1 0x02
118 #define DMA_ADDR_2 0x04
119 #define DMA_ADDR_3 0x06
120 #define DMA_ADDR_4 0xC0
121 #define DMA_ADDR_5 0xC4
122 #define DMA_ADDR_6 0xC8
123 #define DMA_ADDR_7 0xCC
125 #define DMA_CNT_0 0x01 /* DMA count registers */
126 #define DMA_CNT_1 0x03
127 #define DMA_CNT_2 0x05
128 #define DMA_CNT_3 0x07
129 #define DMA_CNT_4 0xC2
130 #define DMA_CNT_5 0xC6
131 #define DMA_CNT_6 0xCA
132 #define DMA_CNT_7 0xCE
134 #define DMA_LO_PAGE_0 0x87 /* DMA page registers */
135 #define DMA_LO_PAGE_1 0x83
136 #define DMA_LO_PAGE_2 0x81
137 #define DMA_LO_PAGE_3 0x82
138 #define DMA_LO_PAGE_5 0x8B
139 #define DMA_LO_PAGE_6 0x89
140 #define DMA_LO_PAGE_7 0x8A
142 #define DMA_HI_PAGE_0 0x487 /* DMA page registers */
143 #define DMA_HI_PAGE_1 0x483
144 #define DMA_HI_PAGE_2 0x481
145 #define DMA_HI_PAGE_3 0x482
146 #define DMA_HI_PAGE_5 0x48B
147 #define DMA_HI_PAGE_6 0x489
148 #define DMA_HI_PAGE_7 0x48A
150 #define DMA1_EXT_REG 0x40B
151 #define DMA2_EXT_REG 0x4D6
158 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
159 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
162 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
164 #define DMA_AUTOINIT 0x10
183 unsigned char ucDmaCmd = 0x00; in enable_dma()
186 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */ in enable_dma()
206 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
215 dma_outb(0, DMA1_CLEAR_FF_REG); in clear_dma_ff()
217 dma_outb(0, DMA2_CLEAR_FF_REG); in clear_dma_ff()
237 case 0: in set_dma_page()
254 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5); in set_dma_page()
258 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6); in set_dma_page()
262 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7); in set_dma_page()
274 dma_outb(phys & 0xff, in set_dma_addr()
276 dma_outb((phys >> 8) & 0xff, in set_dma_addr()
279 dma_outb((phys >> 1) & 0xff, in set_dma_addr()
281 dma_outb((phys >> 9) & 0xff, in set_dma_addr()
300 dma_outb(count & 0xff, in set_dma_count()
302 dma_outb((count >> 8) & 0xff, in set_dma_count()
305 dma_outb((count >> 1) & 0xff, in set_dma_count()
307 dma_outb((count >> 9) & 0xff, in set_dma_count()
346 #define isa_dma_bridge_buggy (0)