Lines Matching +full:bus +full:- +full:range
1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * Common pmac/prep/chrp pci routines. -- Cort
36 #include <asm/pci-bridge.h>
39 #include <asm/ppc-pci.h>
71 int ret, phb_id = -1; in get_phb_number()
76 * the respective device-tree properties. Firstly, try reading in get_phb_number()
77 * standard "linux,pci-domain", then try reading "ibm,opal-phbid" in get_phb_number()
78 * (only present in powernv OPAL environment), then try device-tree in get_phb_number()
87 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop); in get_phb_number()
103 phb_id = (int)(prop & (MAX_PHBS - 1)); in get_phb_number()
130 phb->global_number = get_phb_number(dev); in pcibios_alloc_controller()
133 list_add_tail(&phb->list_node, &hose_list); in pcibios_alloc_controller()
136 phb->dn = dev; in pcibios_alloc_controller()
137 phb->is_dynamic = slab_is_available(); in pcibios_alloc_controller()
157 if (phb->global_number < MAX_PHBS) in pcibios_free_controller()
158 clear_bit(phb->global_number, phb_bitmap); in pcibios_free_controller()
160 list_del(&phb->list_node); in pcibios_free_controller()
163 if (phb->is_dynamic) in pcibios_free_controller()
175 * The callback occurs when all references to the root bus
179 * which is associated with the 'struct pci_controller.bus'
180 * (root bus) - it expects .release_data to hold a pointer
196 bridge->release_data; in pcibios_free_controller_deferred()
198 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic); in pcibios_free_controller_deferred()
210 resource_size_t pcibios_window_alignment(struct pci_bus *bus, in pcibios_window_alignment() argument
213 struct pci_controller *phb = pci_bus_to_host(bus); in pcibios_window_alignment()
215 if (phb->controller_ops.window_alignment) in pcibios_window_alignment()
216 return phb->controller_ops.window_alignment(bus, type); in pcibios_window_alignment()
226 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) in pcibios_setup_bridge() argument
228 struct pci_controller *hose = pci_bus_to_host(bus); in pcibios_setup_bridge()
230 if (hose->controller_ops.setup_bridge) in pcibios_setup_bridge()
231 hose->controller_ops.setup_bridge(bus, type); in pcibios_setup_bridge()
236 struct pci_controller *phb = pci_bus_to_host(dev->bus); in pcibios_reset_secondary_bus()
238 if (phb->controller_ops.reset_secondary_bus) { in pcibios_reset_secondary_bus()
239 phb->controller_ops.reset_secondary_bus(dev); in pcibios_reset_secondary_bus()
284 return hose->pci_io_size; in pcibios_io_size()
286 return resource_size(&hose->io_resource); in pcibios_io_size()
299 if (address >= hose->io_base_virt && in pcibios_vaddr_is_ioport()
300 address < (hose->io_base_virt + size)) { in pcibios_vaddr_is_ioport()
318 if (address >= hose->io_base_phys && in pci_address_to_pio()
319 address < (hose->io_base_phys + size)) { in pci_address_to_pio()
321 (unsigned long)hose->io_base_virt - _IO_BASE; in pci_address_to_pio()
322 ret = base + (address - hose->io_base_phys); in pci_address_to_pio()
333 * Return the domain number for this bus.
335 int pci_domain_nr(struct pci_bus *bus) in pci_domain_nr() argument
337 struct pci_controller *hose = pci_bus_to_host(bus); in pci_domain_nr()
339 return hose->global_number; in pci_domain_nr()
344 * PCI bus numbers have not yet been assigned, and you need to
355 if (hose->dn == node) in pci_find_hose_for_OF_device()
357 node = node->parent; in pci_find_hose_for_OF_device()
367 if (hose->global_number == domain_nr) in pci_find_controller_for_domain()
384 /* Try to get a mapping from the device-tree */ in pci_read_irq_line()
397 return -1; in pci_read_irq_line()
399 return -1; in pci_read_irq_line()
402 return -1; in pci_read_irq_line()
414 return -1; in pci_read_irq_line()
419 pci_dev->irq = virq; in pci_read_irq_line()
425 * Platform support for /proc/bus/pci/X/Y mmap()s.
426 * -- paulus.
430 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pci_iobar_pfn()
434 return -EINVAL; in pci_iobar_pfn()
437 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; in pci_iobar_pfn()
439 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; in pci_iobar_pfn()
464 struct resource *rp = &pdev->resource[i]; in pci_phys_mem_access_prot()
465 int flags = rp->flags; in pci_phys_mem_access_prot()
470 /* In the range of this resource? */ in pci_phys_mem_access_prot()
471 if (offset < (rp->start & PAGE_MASK) || in pci_phys_mem_access_prot()
472 offset > rp->end) in pci_phys_mem_access_prot()
481 if (found->flags & IORESOURCE_PREFETCH) in pci_phys_mem_access_prot()
486 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", in pci_phys_mem_access_prot()
492 /* This provides legacy IO read access on a bus */
493 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) in pci_legacy_read() argument
496 struct pci_controller *hose = pci_bus_to_host(bus); in pci_legacy_read()
497 struct resource *rp = &hose->io_resource; in pci_legacy_read()
500 /* Check if port can be supported by that bus. We only check in pci_legacy_read()
501 * the ranges of the PHB though, not the bus itself as the rules in pci_legacy_read()
505 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_read()
508 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_read()
509 return -ENXIO; in pci_legacy_read()
510 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_read()
511 return -ENXIO; in pci_legacy_read()
512 addr = hose->io_base_virt + port; in pci_legacy_read()
520 return -EINVAL; in pci_legacy_read()
525 return -EINVAL; in pci_legacy_read()
529 return -EINVAL; in pci_legacy_read()
532 /* This provides legacy IO write access on a bus */
533 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) in pci_legacy_write() argument
536 struct pci_controller *hose = pci_bus_to_host(bus); in pci_legacy_write()
537 struct resource *rp = &hose->io_resource; in pci_legacy_write()
540 /* Check if port can be supported by that bus. We only check in pci_legacy_write()
541 * the ranges of the PHB though, not the bus itself as the rules in pci_legacy_write()
545 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_write()
548 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_write()
549 return -ENXIO; in pci_legacy_write()
550 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_write()
551 return -ENXIO; in pci_legacy_write()
552 addr = hose->io_base_virt + port; in pci_legacy_write()
565 return -EINVAL; in pci_legacy_write()
570 return -EINVAL; in pci_legacy_write()
574 return -EINVAL; in pci_legacy_write()
577 /* This provides legacy IO or memory mmap access on a bus */
578 int pci_mmap_legacy_page_range(struct pci_bus *bus, in pci_mmap_legacy_page_range() argument
582 struct pci_controller *hose = pci_bus_to_host(bus); in pci_mmap_legacy_page_range()
584 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; in pci_mmap_legacy_page_range()
585 resource_size_t size = vma->vm_end - vma->vm_start; in pci_mmap_legacy_page_range()
589 pci_domain_nr(bus), bus->number, in pci_mmap_legacy_page_range()
592 (unsigned long long)(offset + size - 1)); in pci_mmap_legacy_page_range()
602 if ((offset + size) > hose->isa_mem_size) { in pci_mmap_legacy_page_range()
604 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", in pci_mmap_legacy_page_range()
605 current->comm, current->pid, pci_domain_nr(bus), bus->number); in pci_mmap_legacy_page_range()
606 if (vma->vm_flags & VM_SHARED) in pci_mmap_legacy_page_range()
610 offset += hose->isa_mem_phys; in pci_mmap_legacy_page_range()
612 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_mmap_legacy_page_range()
614 rp = &hose->io_resource; in pci_mmap_legacy_page_range()
615 if (!(rp->flags & IORESOURCE_IO)) in pci_mmap_legacy_page_range()
616 return -ENXIO; in pci_mmap_legacy_page_range()
617 if (roffset < rp->start || (roffset + size) > rp->end) in pci_mmap_legacy_page_range()
618 return -ENXIO; in pci_mmap_legacy_page_range()
619 offset += hose->io_base_phys; in pci_mmap_legacy_page_range()
621 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); in pci_mmap_legacy_page_range()
623 vma->vm_pgoff = offset >> PAGE_SHIFT; in pci_mmap_legacy_page_range()
624 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); in pci_mmap_legacy_page_range()
625 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, in pci_mmap_legacy_page_range()
626 vma->vm_end - vma->vm_start, in pci_mmap_legacy_page_range()
627 vma->vm_page_prot); in pci_mmap_legacy_page_range()
636 if (rsrc->flags & IORESOURCE_IO) { in pci_resource_to_user()
637 pcibios_resource_to_bus(dev->bus, ®ion, in pci_resource_to_user()
648 * That means we may have 64-bit values where some apps only expect in pci_resource_to_user()
649 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). in pci_resource_to_user()
651 *start = rsrc->start; in pci_resource_to_user()
652 *end = rsrc->end; in pci_resource_to_user()
656 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
659 * @primary: set if primary bus (32 bits only, soon to be deprecated)
668 * - We can only cope with one IO space range and up to 3 Memory space
672 * - Some busses have IO space not starting at 0, which causes trouble with
676 * - Some 32 bits platforms such as 4xx can have physical space larger than
684 struct of_pci_range range; in pci_process_bridge_OF_ranges() local
695 for_each_of_pci_range(&parser, &range) { in pci_process_bridge_OF_ranges()
696 /* If we failed translation or got a zero-sized region in pci_process_bridge_OF_ranges()
701 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) in pci_process_bridge_OF_ranges()
706 switch (range.flags & IORESOURCE_TYPE_BITS) { in pci_process_bridge_OF_ranges()
709 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", in pci_process_bridge_OF_ranges()
710 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
711 range.pci_addr); in pci_process_bridge_OF_ranges()
713 /* We support only one IO range */ in pci_process_bridge_OF_ranges()
714 if (hose->pci_io_size) { in pci_process_bridge_OF_ranges()
716 " \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
721 if (range.size > 0x01000000) in pci_process_bridge_OF_ranges()
722 range.size = 0x01000000; in pci_process_bridge_OF_ranges()
725 hose->io_base_virt = ioremap(range.cpu_addr, in pci_process_bridge_OF_ranges()
726 range.size); in pci_process_bridge_OF_ranges()
731 (unsigned long)hose->io_base_virt; in pci_process_bridge_OF_ranges()
736 hose->pci_io_size = range.pci_addr + range.size; in pci_process_bridge_OF_ranges()
737 hose->io_base_phys = range.cpu_addr - range.pci_addr; in pci_process_bridge_OF_ranges()
740 res = &hose->io_resource; in pci_process_bridge_OF_ranges()
741 range.cpu_addr = range.pci_addr; in pci_process_bridge_OF_ranges()
745 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", in pci_process_bridge_OF_ranges()
746 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
747 range.pci_addr, in pci_process_bridge_OF_ranges()
748 (range.flags & IORESOURCE_PREFETCH) ? in pci_process_bridge_OF_ranges()
754 " \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
758 if (range.pci_addr == 0) { in pci_process_bridge_OF_ranges()
760 isa_mem_base = range.cpu_addr; in pci_process_bridge_OF_ranges()
761 hose->isa_mem_phys = range.cpu_addr; in pci_process_bridge_OF_ranges()
762 hose->isa_mem_size = range.size; in pci_process_bridge_OF_ranges()
766 hose->mem_offset[memno] = range.cpu_addr - in pci_process_bridge_OF_ranges()
767 range.pci_addr; in pci_process_bridge_OF_ranges()
768 res = &hose->mem_resources[memno++]; in pci_process_bridge_OF_ranges()
772 res->name = dev->full_name; in pci_process_bridge_OF_ranges()
773 res->flags = range.flags; in pci_process_bridge_OF_ranges()
774 res->start = range.cpu_addr; in pci_process_bridge_OF_ranges()
775 res->end = range.cpu_addr + range.size - 1; in pci_process_bridge_OF_ranges()
776 res->parent = res->child = res->sibling = NULL; in pci_process_bridge_OF_ranges()
782 int pci_proc_domain(struct pci_bus *bus) in pci_proc_domain() argument
784 struct pci_controller *hose = pci_bus_to_host(bus); in pci_proc_domain()
789 return hose->global_number != 0; in pci_proc_domain()
806 struct pci_controller *hose = pci_bus_to_host(dev->bus); in pcibios_fixup_resources()
815 if (dev->is_virtfn) in pcibios_fixup_resources()
819 struct resource *res = dev->resource + i; in pcibios_fixup_resources()
821 if (!res->flags) in pcibios_fixup_resources()
824 /* If we're going to re-assign everything, we mark all resources in pcibios_fixup_resources()
825 * as unset (and 0-base them). In addition, we mark BARs starting in pcibios_fixup_resources()
827 * since in that case, we don't want to re-assign anything in pcibios_fixup_resources()
829 pcibios_resource_to_bus(dev->bus, ®, res); in pcibios_fixup_resources()
832 /* Only print message if not re-assigning */ in pcibios_fixup_resources()
836 res->end -= res->start; in pcibios_fixup_resources()
837 res->start = 0; in pcibios_fixup_resources()
838 res->flags |= IORESOURCE_UNSET; in pcibios_fixup_resources()
854 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
856 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, in pcibios_uninitialized_bridge_resource() argument
859 struct pci_controller *hose = pci_bus_to_host(bus); in pcibios_uninitialized_bridge_resource()
860 struct pci_dev *dev = bus->self; in pcibios_uninitialized_bridge_resource()
871 if (res->flags & IORESOURCE_MEM) { in pcibios_uninitialized_bridge_resource()
872 pcibios_resource_to_bus(dev->bus, ®ion, res); in pcibios_uninitialized_bridge_resource()
874 /* If the BAR is non-0 then it's probably been initialized */ in pcibios_uninitialized_bridge_resource()
890 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && in pcibios_uninitialized_bridge_resource()
891 hose->mem_resources[i].start == hose->mem_offset[i]) in pcibios_uninitialized_bridge_resource()
900 /* If the BAR is non-0, then we consider it assigned */ in pcibios_uninitialized_bridge_resource()
901 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pcibios_uninitialized_bridge_resource()
902 if (((res->start - offset) & 0xfffffffful) != 0) in pcibios_uninitialized_bridge_resource()
906 * starting at low addresses -is- valid. What we do instead if that in pcibios_uninitialized_bridge_resource()
921 /* Fixup resources of a PCI<->PCI bridge */
922 static void pcibios_fixup_bridge(struct pci_bus *bus) in pcibios_fixup_bridge() argument
927 struct pci_dev *dev = bus->self; in pcibios_fixup_bridge()
929 pci_bus_for_each_resource(bus, res, i) { in pcibios_fixup_bridge()
930 if (!res || !res->flags) in pcibios_fixup_bridge()
932 if (i >= 3 && bus->self->transparent) in pcibios_fixup_bridge()
940 res->flags |= IORESOURCE_UNSET; in pcibios_fixup_bridge()
941 res->start = 0; in pcibios_fixup_bridge()
942 res->end = -1; in pcibios_fixup_bridge()
946 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res); in pcibios_fixup_bridge()
949 * and clear them out so they get re-assigned later in pcibios_fixup_bridge()
951 if (pcibios_uninitialized_bridge_resource(bus, res)) { in pcibios_fixup_bridge()
952 res->flags = 0; in pcibios_fixup_bridge()
958 void pcibios_setup_bus_self(struct pci_bus *bus) in pcibios_setup_bus_self() argument
962 /* Fix up the bus resources for P2P bridges */ in pcibios_setup_bus_self()
963 if (bus->self != NULL) in pcibios_setup_bus_self()
964 pcibios_fixup_bridge(bus); in pcibios_setup_bus_self()
966 /* Platform specific bus fixups. This is currently only used in pcibios_setup_bus_self()
970 ppc_md.pcibios_fixup_bus(bus); in pcibios_setup_bus_self()
972 /* Setup bus DMA mappings */ in pcibios_setup_bus_self()
973 phb = pci_bus_to_host(bus); in pcibios_setup_bus_self()
974 if (phb->controller_ops.dma_bus_setup) in pcibios_setup_bus_self()
975 phb->controller_ops.dma_bus_setup(bus); in pcibios_setup_bus_self()
984 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); in pcibios_bus_add_device()
987 set_dma_ops(&dev->dev, pci_dma_ops); in pcibios_bus_add_device()
988 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET; in pcibios_bus_add_device()
991 phb = pci_bus_to_host(dev->bus); in pcibios_bus_add_device()
992 if (phb->controller_ops.dma_dev_setup) in pcibios_bus_add_device()
993 phb->controller_ops.dma_dev_setup(dev); in pcibios_bus_add_device()
1016 /* No special bus mastering setup handling */ in pcibios_set_master()
1019 void pcibios_fixup_bus(struct pci_bus *bus) in pcibios_fixup_bus() argument
1021 /* When called from the generic PCI probe, read PCI<->PCI bridge in pcibios_fixup_bus()
1022 * bases. This is -not- called when generating the PCI tree from in pcibios_fixup_bus()
1023 * the OF device-tree. in pcibios_fixup_bus()
1025 pci_read_bridge_bases(bus); in pcibios_fixup_bus()
1027 /* Now fixup the bus bus */ in pcibios_fixup_bus()
1028 pcibios_setup_bus_self(bus); in pcibios_fixup_bus()
1035 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) in skip_isa_ioresource_align()
1043 * addresses to be allocated in the 0x000-0x0ff region
1047 * the low 10 bits of the IO address. The 0x00-0xff region
1049 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1050 * but we want to try to avoid allocating at 0x2900-0x2bff
1051 * which might have be mirrored at 0x0100-0x03ff..
1057 resource_size_t start = res->start; in pcibios_align_resource()
1059 if (res->flags & IORESOURCE_IO) { in pcibios_align_resource()
1080 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { in reparent_resources()
1081 if (p->end < res->start) in reparent_resources()
1083 if (res->end < p->start) in reparent_resources()
1085 if (p->start < res->start || p->end > res->end) in reparent_resources()
1086 return -1; /* not completely contained */ in reparent_resources()
1091 return -1; /* didn't find any conflicting entries? */ in reparent_resources()
1092 res->parent = parent; in reparent_resources()
1093 res->child = *firstpp; in reparent_resources()
1094 res->sibling = *pp; in reparent_resources()
1097 for (p = res->child; p != NULL; p = p->sibling) { in reparent_resources()
1098 p->parent = res; in reparent_resources()
1100 p->name, p, res->name); in reparent_resources()
1108 * On the other hand, we cannot just re-allocate all devices, as it would
1114 * - I/O or memory regions not configured
1115 * - regions configured, but not enabled in the command register
1116 * - bogus I/O addresses above 64K used
1117 * - expansion ROMs left enabled (this may sound harmless, but given
1123 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1138 static void pcibios_allocate_bus_resources(struct pci_bus *bus) in pcibios_allocate_bus_resources() argument
1144 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", in pcibios_allocate_bus_resources()
1145 pci_domain_nr(bus), bus->number); in pcibios_allocate_bus_resources()
1147 pci_bus_for_each_resource(bus, res, i) { in pcibios_allocate_bus_resources()
1148 if (!res || !res->flags || res->start > res->end || res->parent) in pcibios_allocate_bus_resources()
1152 if (res->flags & IORESOURCE_UNSET) in pcibios_allocate_bus_resources()
1155 if (bus->parent == NULL) in pcibios_allocate_bus_resources()
1156 pr = (res->flags & IORESOURCE_IO) ? in pcibios_allocate_bus_resources()
1159 pr = pci_find_parent_resource(bus->self, res); in pcibios_allocate_bus_resources()
1163 * bridge is transparent -- paulus in pcibios_allocate_bus_resources()
1169 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n", in pcibios_allocate_bus_resources()
1170 bus->self ? pci_name(bus->self) : "PHB", bus->number, in pcibios_allocate_bus_resources()
1171 i, res, pr, (pr && pr->name) ? pr->name : "nil"); in pcibios_allocate_bus_resources()
1173 if (pr && !(pr->flags & IORESOURCE_UNSET)) { in pcibios_allocate_bus_resources()
1174 struct pci_dev *dev = bus->self; in pcibios_allocate_bus_resources()
1192 i, bus->number); in pcibios_allocate_bus_resources()
1200 res->start = 0; in pcibios_allocate_bus_resources()
1201 res->end = -1; in pcibios_allocate_bus_resources()
1202 res->flags = 0; in pcibios_allocate_bus_resources()
1205 list_for_each_entry(b, &bus->children, node) in pcibios_allocate_bus_resources()
1211 struct resource *pr, *r = &dev->resource[idx]; in alloc_resource()
1217 if (!pr || (pr->flags & IORESOURCE_UNSET) || in alloc_resource()
1224 r->flags |= IORESOURCE_UNSET; in alloc_resource()
1225 r->end -= r->start; in alloc_resource()
1226 r->start = 0; in alloc_resource()
1240 r = &dev->resource[idx]; in pcibios_allocate_resources()
1241 if (r->parent) /* Already allocated */ in pcibios_allocate_resources()
1243 if (!r->flags || (r->flags & IORESOURCE_UNSET)) in pcibios_allocate_resources()
1250 if (r->flags & IORESOURCE_IO) in pcibios_allocate_resources()
1259 r = &dev->resource[PCI_ROM_RESOURCE]; in pcibios_allocate_resources()
1260 if (r->flags) { in pcibios_allocate_resources()
1265 pci_read_config_dword(dev, dev->rom_base_reg, ®); in pcibios_allocate_resources()
1269 r->flags &= ~IORESOURCE_ROM_ENABLE; in pcibios_allocate_resources()
1270 pci_write_config_dword(dev, dev->rom_base_reg, in pcibios_allocate_resources()
1277 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) in pcibios_reserve_legacy_regions() argument
1279 struct pci_controller *hose = pci_bus_to_host(bus); in pcibios_reserve_legacy_regions()
1284 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); in pcibios_reserve_legacy_regions()
1287 if (!(hose->io_resource.flags & IORESOURCE_IO)) in pcibios_reserve_legacy_regions()
1289 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pcibios_reserve_legacy_regions()
1292 res->name = "Legacy IO"; in pcibios_reserve_legacy_regions()
1293 res->flags = IORESOURCE_IO; in pcibios_reserve_legacy_regions()
1294 res->start = offset; in pcibios_reserve_legacy_regions()
1295 res->end = (offset + 0xfff) & 0xfffffffful; in pcibios_reserve_legacy_regions()
1297 if (request_resource(&hose->io_resource, res)) { in pcibios_reserve_legacy_regions()
1300 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
1307 pres = &hose->mem_resources[i]; in pcibios_reserve_legacy_regions()
1308 offset = hose->mem_offset[i]; in pcibios_reserve_legacy_regions()
1309 if (!(pres->flags & IORESOURCE_MEM)) in pcibios_reserve_legacy_regions()
1312 if ((pres->start - offset) <= 0xa0000 && in pcibios_reserve_legacy_regions()
1313 (pres->end - offset) >= 0xbffff) in pcibios_reserve_legacy_regions()
1320 res->name = "Legacy VGA memory"; in pcibios_reserve_legacy_regions()
1321 res->flags = IORESOURCE_MEM; in pcibios_reserve_legacy_regions()
1322 res->start = 0xa0000 + offset; in pcibios_reserve_legacy_regions()
1323 res->end = 0xbffff + offset; in pcibios_reserve_legacy_regions()
1328 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
1347 * bus available resources to avoid allocating things on top of them in pcibios_resource_survey()
1365 * rest of the code later, for now, keep it as-is as our main
1366 * resource allocation function doesn't deal with sub-trees yet.
1368 void pcibios_claim_one_bus(struct pci_bus *bus) in pcibios_claim_one_bus() argument
1373 list_for_each_entry(dev, &bus->devices, bus_list) { in pcibios_claim_one_bus()
1377 struct resource *r = &dev->resource[i]; in pcibios_claim_one_bus()
1379 if (r->parent || !r->start || !r->flags) in pcibios_claim_one_bus()
1392 list_for_each_entry(child_bus, &bus->children, node) in pcibios_claim_one_bus()
1401 * added to a bus, this include calling it for a PHB that is just
1404 void pcibios_finish_adding_to_bus(struct pci_bus *bus) in pcibios_finish_adding_to_bus() argument
1406 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", in pcibios_finish_adding_to_bus()
1407 pci_domain_nr(bus), bus->number); in pcibios_finish_adding_to_bus()
1409 /* Allocate bus and devices resources */ in pcibios_finish_adding_to_bus()
1410 pcibios_allocate_bus_resources(bus); in pcibios_finish_adding_to_bus()
1411 pcibios_claim_one_bus(bus); in pcibios_finish_adding_to_bus()
1413 if (bus->self) in pcibios_finish_adding_to_bus()
1414 pci_assign_unassigned_bridge_resources(bus->self); in pcibios_finish_adding_to_bus()
1416 pci_assign_unassigned_bus_resources(bus); in pcibios_finish_adding_to_bus()
1420 pci_bus_add_devices(bus); in pcibios_finish_adding_to_bus()
1426 struct pci_controller *phb = pci_bus_to_host(dev->bus); in pcibios_enable_device()
1428 if (phb->controller_ops.enable_device_hook) in pcibios_enable_device()
1429 if (!phb->controller_ops.enable_device_hook(dev)) in pcibios_enable_device()
1430 return -EINVAL; in pcibios_enable_device()
1437 struct pci_controller *phb = pci_bus_to_host(dev->bus); in pcibios_disable_device()
1439 if (phb->controller_ops.disable_device) in pcibios_disable_device()
1440 phb->controller_ops.disable_device(dev); in pcibios_disable_device()
1445 return (unsigned long) hose->io_base_virt - _IO_BASE; in pcibios_io_space_offset()
1456 res = &hose->io_resource; in pcibios_setup_phb_resources()
1458 if (!res->flags) { in pcibios_setup_phb_resources()
1461 hose->dn, hose->global_number); in pcibios_setup_phb_resources()
1472 res = &hose->mem_resources[i]; in pcibios_setup_phb_resources()
1473 if (!res->flags) in pcibios_setup_phb_resources()
1476 offset = hose->mem_offset[i]; in pcibios_setup_phb_resources()
1496 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, in null_read_config() argument
1503 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, in null_write_config() argument
1522 static struct pci_bus bus; in fake_pci_bus() local
1525 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); in fake_pci_bus()
1527 bus.number = busnr; in fake_pci_bus()
1528 bus.sysdata = hose; in fake_pci_bus()
1529 bus.ops = hose? hose->ops: &null_pci_ops; in fake_pci_bus()
1530 return &bus; in fake_pci_bus()
1534 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1537 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1548 int early_find_capability(struct pci_controller *hose, int bus, int devfn, in EARLY_PCI_OP()
1551 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); in EARLY_PCI_OP()
1554 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) in pcibios_get_phb_of_node() argument
1556 struct pci_controller *hose = bus->sysdata; in pcibios_get_phb_of_node()
1558 return of_node_get(hose->dn); in pcibios_get_phb_of_node()
1562 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1568 struct pci_bus *bus; in pcibios_scan_phb() local
1569 struct device_node *node = hose->dn; in pcibios_scan_phb()
1577 /* Wire up PHB bus resources */ in pcibios_scan_phb()
1580 hose->busn.start = hose->first_busno; in pcibios_scan_phb()
1581 hose->busn.end = hose->last_busno; in pcibios_scan_phb()
1582 hose->busn.flags = IORESOURCE_BUS; in pcibios_scan_phb()
1583 pci_add_resource(&resources, &hose->busn); in pcibios_scan_phb()
1585 /* Create an empty bus for the toplevel */ in pcibios_scan_phb()
1586 bus = pci_create_root_bus(hose->parent, hose->first_busno, in pcibios_scan_phb()
1587 hose->ops, hose, &resources); in pcibios_scan_phb()
1588 if (bus == NULL) { in pcibios_scan_phb()
1589 pr_err("Failed to create bus for PCI domain %04x\n", in pcibios_scan_phb()
1590 hose->global_number); in pcibios_scan_phb()
1594 hose->bus = bus; in pcibios_scan_phb()
1598 if (node && hose->controller_ops.probe_mode) in pcibios_scan_phb()
1599 mode = hose->controller_ops.probe_mode(bus); in pcibios_scan_phb()
1602 of_scan_bus(node, bus); in pcibios_scan_phb()
1605 pci_bus_update_busn_res_end(bus, 255); in pcibios_scan_phb()
1606 hose->last_busno = pci_scan_child_bus(bus); in pcibios_scan_phb()
1607 pci_bus_update_busn_res_end(bus, hose->last_busno); in pcibios_scan_phb()
1617 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { in pcibios_scan_phb()
1619 list_for_each_entry(child, &bus->children, node) in pcibios_scan_phb()
1627 int i, class = dev->class >> 8; in fixup_hide_host_resource_fsl()
1629 int prog_if = dev->class & 0xf; in fixup_hide_host_resource_fsl()
1633 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && in fixup_hide_host_resource_fsl()
1635 (dev->bus->parent == NULL)) { in fixup_hide_host_resource_fsl()
1637 dev->resource[i].start = 0; in fixup_hide_host_resource_fsl()
1638 dev->resource[i].end = 0; in fixup_hide_host_resource_fsl()
1639 dev->resource[i].flags = 0; in fixup_hide_host_resource_fsl()