50 #define CPM_MAP_SIZE    (0x4000)
104 	pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);  in cpm_pic_host_map()
108 	return 0;  in cpm_pic_host_map()
130 	unsigned int sirq = 0, hwirq, eirq;  in cpm_pic_init()
143 	ret = of_address_to_resource(np, 0, &res);  in cpm_pic_init()
151 	sirq = irq_of_parse_and_map(np, 0);  in cpm_pic_init()
161 	out_be32(&cpic_reg->cpic_cimr, 0);  in cpm_pic_init()
166 		sirq = 0;  in cpm_pic_init()
179 	eirq = irq_of_parse_and_map(np, 0);  in cpm_pic_init()
220 	if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */  in cpm_reset()
221 		out_be32(&siu_conf->sc_sdcr, 0x40);  in cpm_reset()
236 	if (command & 0xffffff0f)  in cpm_command()
241 	ret = 0;  in cpm_command()
243 	for (i = 0; i < MAX_CR_CMD_LOOPS; i++)  in cpm_command()
244 		if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)  in cpm_command()
347 	if (port != 0)  in cpm1_set_pin16()
389 	int i, bits = 0;  in cpm1_clk_setup()
394 		{CPM_CLK_SCC1, CPM_BRG1, 0},  in cpm1_clk_setup()
403 		{CPM_CLK_SCC2, CPM_BRG1, 0},  in cpm1_clk_setup()
412 		{CPM_CLK_SCC3, CPM_BRG1, 0},  in cpm1_clk_setup()
421 		{CPM_CLK_SCC4, CPM_BRG1, 0},  in cpm1_clk_setup()
430 		{CPM_CLK_SMC1, CPM_BRG1, 0},  in cpm1_clk_setup()
439 		{CPM_CLK_SMC2, CPM_BRG1, 0},  in cpm1_clk_setup()
452 		shift = 0;  in cpm1_clk_setup()
485 	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {  in cpm1_clk_setup()
486 		if (clk_map[i][0] == target && clk_map[i][1] == clock) {  in cpm1_clk_setup()
512 	return 0;  in cpm1_clk_setup()
602 	return 0;  in cpm1_gpio16_dir_out()
619 	return 0;  in cpm1_gpio16_dir_in()
639 		for (i = 0, j = 0; i < 16; i++)  in cpm1_gpiochip_add16()
731 	return 0;  in cpm1_gpio32_dir_out()
748 	return 0;  in cpm1_gpio32_dir_in()