Lines Matching +full:pcie +full:- +full:mem
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC83xx/85xx/86xx PCI/PCIE support routing.
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
6 * Copyright 2008-2009 MontaVista Software, Inc.
11 * Roy Zang <tie-fei.zang@freescale.com>
12 * MPC83xx PCI-Express support:
33 #include <asm/pci-bridge.h>
34 #include <asm/ppc-pci.h>
38 #include <asm/ppc-opcode.h>
49 /* if we aren't a PCIe don't bother */ in quirk_fsl_pcie_early()
58 dev->class = PCI_CLASS_BRIDGE_PCI << 8; in quirk_fsl_pcie_early()
70 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { in fsl_pcie_check_link()
71 if (hose->ops->read == fsl_indirect_read_config) in fsl_pcie_check_link()
72 __indirect_read_config(hose, hose->first_busno, 0, in fsl_pcie_check_link()
79 struct ccsr_pci __iomem *pci = hose->private_data; in fsl_pcie_check_link()
80 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ in fsl_pcie_check_link()
81 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) in fsl_pcie_check_link()
96 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; in fsl_indirect_read_config()
98 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; in fsl_indirect_read_config()
116 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pci_dma_dev_setup_swiotlb()
118 pdev->dev.bus_dma_limit = in pci_dma_dev_setup_swiotlb()
119 hose->dma_window_base_cur + hose->dma_window_size - 1; in pci_dma_dev_setup_swiotlb()
125 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb; in setup_swiotlb_ops()
137 if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) { in fsl_pci_dma_set_mask()
138 dev->bus_dma_limit = 0; in fsl_pci_dma_set_mask()
139 dev->archdata.dma_offset = pci64_dma_offset; in fsl_pci_dma_set_mask()
147 resource_size_t pci_addr = res->start - offset; in setup_one_atmu()
148 resource_size_t phys_addr = res->start; in setup_one_atmu()
150 u32 flags = 0x80044000; /* enable & mem R/W */ in setup_one_atmu()
153 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", in setup_one_atmu()
154 (u64)res->start, (u64)size); in setup_one_atmu()
156 if (res->flags & IORESOURCE_PREFETCH) in setup_one_atmu()
164 return -1; in setup_one_atmu()
166 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); in setup_one_atmu()
167 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); in setup_one_atmu()
168 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); in setup_one_atmu()
169 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); in setup_one_atmu()
173 size -= (resource_size_t)1U << bits; in setup_one_atmu()
189 return of_property_read_bool(node, "linux,usable-memory"); in is_kdump()
192 /* atmu setup for fsl pci/pcie controller */
195 struct ccsr_pci __iomem *pci = hose->private_data; in setup_pci_atmu()
197 u64 mem, sz, paddr_hi = 0; in setup_pci_atmu() local
208 * errors by closing the window on in-flight DMA. in setup_pci_atmu()
211 * hose->dma_window_size still get set. in setup_pci_atmu()
215 if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) { in setup_pci_atmu()
229 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { in setup_pci_atmu()
238 out_be32(&pci->pow[i].powar, 0); in setup_pci_atmu()
242 out_be32(&pci->piw[i].piwar, 0); in setup_pci_atmu()
245 /* Setup outbound MEM window */ in setup_pci_atmu()
247 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) in setup_pci_atmu()
250 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); in setup_pci_atmu()
251 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); in setup_pci_atmu()
254 offset = hose->mem_offset[i]; in setup_pci_atmu()
255 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset); in setup_pci_atmu()
259 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; in setup_pci_atmu()
265 if (hose->io_resource.flags & IORESOURCE_IO) { in setup_pci_atmu()
271 (u64)hose->io_resource.start, in setup_pci_atmu()
272 (u64)resource_size(&hose->io_resource), in setup_pci_atmu()
273 (u64)hose->io_base_phys); in setup_pci_atmu()
274 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); in setup_pci_atmu()
275 out_be32(&pci->pow[j].potear, 0); in setup_pci_atmu()
276 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); in setup_pci_atmu()
278 out_be32(&pci->pow[j].powar, 0x80088000 in setup_pci_atmu()
279 | (ilog2(hose->io_resource.end in setup_pci_atmu()
280 - hose->io_resource.start + 1) - 1)); in setup_pci_atmu()
285 paddr_hi -= offset; in setup_pci_atmu()
286 paddr_lo -= offset; in setup_pci_atmu()
289 pr_err("%pOF: No outbound window space\n", hose->dn); in setup_pci_atmu()
294 pr_err("%pOF: No space for inbound window\n", hose->dn); in setup_pci_atmu()
303 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || in setup_pci_atmu()
305 pcicsrbar = 0x100000000ull - pcicsrbar_sz; in setup_pci_atmu()
307 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; in setup_pci_atmu()
312 pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar); in setup_pci_atmu()
314 /* Setup inbound mem window */ in setup_pci_atmu()
315 mem = memblock_end_of_DRAM(); in setup_pci_atmu()
316 pr_info("%s: end of DRAM %llx\n", __func__, mem); in setup_pci_atmu()
319 * The msi-address-64 property, if it exists, indicates the physical in setup_pci_atmu()
330 reg = of_get_property(hose->dn, "msi-address-64", &len); in setup_pci_atmu()
334 if ((address >= mem) && (address < (mem + PAGE_SIZE))) { in setup_pci_atmu()
335 pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn); in setup_pci_atmu()
336 mem += PAGE_SIZE; in setup_pci_atmu()
339 pr_warn("%pOF: msi-address-64 address of %llx is " in setup_pci_atmu()
340 "unsupported\n", hose->dn, address); in setup_pci_atmu()
344 sz = min(mem, paddr_lo); in setup_pci_atmu()
347 /* PCIe can overmap inbound & outbound since RX & TX are separated */ in setup_pci_atmu()
349 /* Size window to exact size if power-of-two or one size up */ in setup_pci_atmu()
350 if ((1ull << mem_log) != mem) { in setup_pci_atmu()
352 if ((1ull << mem_log) > mem) in setup_pci_atmu()
354 "greater than memory size\n", hose->dn); in setup_pci_atmu()
357 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); in setup_pci_atmu()
361 out_be32(&pci->piw[win_idx].pitar, 0x00000000); in setup_pci_atmu()
362 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); in setup_pci_atmu()
363 out_be32(&pci->piw[win_idx].piwar, piwar); in setup_pci_atmu()
366 win_idx--; in setup_pci_atmu()
367 hose->dma_window_base_cur = 0x00000000; in setup_pci_atmu()
368 hose->dma_window_size = (resource_size_t)sz; in setup_pci_atmu()
372 * let devices that are 64-bit address capable to work w/o in setup_pci_atmu()
375 if (sz != mem) { in setup_pci_atmu()
376 mem_log = ilog2(mem); in setup_pci_atmu()
378 /* Size window up if we dont fit in exact power-of-2 */ in setup_pci_atmu()
379 if ((1ull << mem_log) != mem) in setup_pci_atmu()
382 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); in setup_pci_atmu()
387 out_be32(&pci->piw[win_idx].pitar, 0x00000000); in setup_pci_atmu()
388 out_be32(&pci->piw[win_idx].piwbear, in setup_pci_atmu()
390 out_be32(&pci->piw[win_idx].piwbar, in setup_pci_atmu()
392 out_be32(&pci->piw[win_idx].piwar, piwar); in setup_pci_atmu()
401 pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn); in setup_pci_atmu()
408 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); in setup_pci_atmu()
409 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); in setup_pci_atmu()
410 out_be32(&pci->piw[win_idx].piwar, in setup_pci_atmu()
411 (piwar | (mem_log - 1))); in setup_pci_atmu()
414 win_idx--; in setup_pci_atmu()
416 sz -= 1ull << mem_log; in setup_pci_atmu()
420 piwar |= (mem_log - 1); in setup_pci_atmu()
423 out_be32(&pci->piw[win_idx].pitar, in setup_pci_atmu()
425 out_be32(&pci->piw[win_idx].piwbar, in setup_pci_atmu()
427 out_be32(&pci->piw[win_idx].piwar, piwar); in setup_pci_atmu()
430 win_idx--; in setup_pci_atmu()
434 hose->dma_window_base_cur = 0x00000000; in setup_pci_atmu()
435 hose->dma_window_size = (resource_size_t)paddr; in setup_pci_atmu()
438 if (hose->dma_window_size < mem) { in setup_pci_atmu()
443 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", in setup_pci_atmu()
444 hose->dn); in setup_pci_atmu()
446 /* adjusting outbound windows could reclaim space in mem map */ in setup_pci_atmu()
451 hose->dn); in setup_pci_atmu()
453 pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn, in setup_pci_atmu()
454 (u64)hose->dma_window_size); in setup_pci_atmu()
488 * has bus->resource[0..4] set, so things are a bit more in fsl_pcibios_fixup_bus()
494 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); in fsl_pcibios_fixup_bus()
496 if (bus->parent == hose->bus && (is_pcie || no_link)) { in fsl_pcibios_fixup_bus()
498 struct resource *res = bus->resource[i]; in fsl_pcibios_fixup_bus()
504 par = &hose->io_resource; in fsl_pcibios_fixup_bus()
506 par = &hose->mem_resources[i-1]; in fsl_pcibios_fixup_bus()
509 res->start = par ? par->start : 0; in fsl_pcibios_fixup_bus()
510 res->end = par ? par->end : 0; in fsl_pcibios_fixup_bus()
511 res->flags = par ? par->flags : 0; in fsl_pcibios_fixup_bus()
529 dev = pdev->dev.of_node; in fsl_add_bridge()
533 return -ENODEV; in fsl_add_bridge()
541 return -ENOMEM; in fsl_add_bridge()
545 bus_range = of_get_property(dev, "bus-range", &len); in fsl_add_bridge()
547 printk(KERN_WARNING "Can't get bus-range for %pOF, assume" in fsl_add_bridge()
553 return -ENOMEM; in fsl_add_bridge()
556 hose->parent = &pdev->dev; in fsl_add_bridge()
557 hose->first_busno = bus_range ? bus_range[0] : 0x0; in fsl_add_bridge()
558 hose->last_busno = bus_range ? bus_range[1] : 0xff; in fsl_add_bridge()
563 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); in fsl_add_bridge()
564 if (!hose->private_data) in fsl_add_bridge()
570 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) in fsl_add_bridge()
571 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; in fsl_add_bridge()
574 /* use fsl_indirect_read_config for PCIe */ in fsl_add_bridge()
575 hose->ops = &fsl_indirect_pcie_ops; in fsl_add_bridge()
576 /* For PCIE read HEADER_TYPE to identify controller mode */ in fsl_add_bridge()
585 !of_property_read_bool(dev, "fsl,pci-agent-force-enum")) in fsl_add_bridge()
593 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | in fsl_add_bridge()
596 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; in fsl_add_bridge()
597 /* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */ in fsl_add_bridge()
598 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) { in fsl_add_bridge()
609 * PCI-X operation is not affected. in fsl_add_bridge()
628 "Firmware bus number: %d->%d\n", in fsl_add_bridge()
629 (unsigned long long)rsrc.start, hose->first_busno, in fsl_add_bridge()
630 hose->last_busno); in fsl_add_bridge()
632 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", in fsl_add_bridge()
633 hose, hose->cfg_addr, hose->cfg_data); in fsl_add_bridge()
648 iounmap(hose->private_data); in fsl_add_bridge()
650 if (((unsigned long)hose->cfg_data & PAGE_MASK) != in fsl_add_bridge()
651 ((unsigned long)hose->cfg_addr & PAGE_MASK)) in fsl_add_bridge()
652 iounmap(hose->cfg_data); in fsl_add_bridge()
653 iounmap(hose->cfg_addr); in fsl_add_bridge()
655 return -ENODEV; in fsl_add_bridge()
677 * With the convention of u-boot, the PCIE outbound window 0 serves
690 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) in mpc83xx_pcie_exclude_device()
694 * PCI-E controller does not check the device number bits and just in mpc83xx_pcie_exclude_device()
697 if (bus->number == hose->first_busno || in mpc83xx_pcie_exclude_device()
698 bus->primary == hose->first_busno) { in mpc83xx_pcie_exclude_device()
704 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) in mpc83xx_pcie_exclude_device()
715 struct mpc83xx_pcie_priv *pcie = hose->dn->data; in mpc83xx_pcie_remap_cfg() local
716 u32 dev_base = bus->number << 24 | devfn << 16; in mpc83xx_pcie_remap_cfg()
726 if (bus->number == hose->first_busno) in mpc83xx_pcie_remap_cfg()
727 return pcie->cfg_type0 + offset; in mpc83xx_pcie_remap_cfg()
729 if (pcie->dev_base == dev_base) in mpc83xx_pcie_remap_cfg()
732 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); in mpc83xx_pcie_remap_cfg()
734 pcie->dev_base = dev_base; in mpc83xx_pcie_remap_cfg()
736 return pcie->cfg_type1 + offset; in mpc83xx_pcie_remap_cfg()
745 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) in mpc83xx_pcie_write_config()
760 struct mpc83xx_pcie_priv *pcie; in mpc83xx_pcie_setup() local
762 int ret = -ENOMEM; in mpc83xx_pcie_setup()
764 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); in mpc83xx_pcie_setup()
765 if (!pcie) in mpc83xx_pcie_setup()
768 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); in mpc83xx_pcie_setup()
769 if (!pcie->cfg_type0) in mpc83xx_pcie_setup()
772 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); in mpc83xx_pcie_setup()
774 /* PCI-E isn't configured. */ in mpc83xx_pcie_setup()
775 ret = -ENODEV; in mpc83xx_pcie_setup()
779 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); in mpc83xx_pcie_setup()
780 if (!pcie->cfg_type1) in mpc83xx_pcie_setup()
783 WARN_ON(hose->dn->data); in mpc83xx_pcie_setup()
784 hose->dn->data = pcie; in mpc83xx_pcie_setup()
785 hose->ops = &mpc83xx_pcie_ops; in mpc83xx_pcie_setup()
786 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; in mpc83xx_pcie_setup()
788 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); in mpc83xx_pcie_setup()
789 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); in mpc83xx_pcie_setup()
792 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; in mpc83xx_pcie_setup()
796 iounmap(pcie->cfg_type0); in mpc83xx_pcie_setup()
798 kfree(pcie); in mpc83xx_pcie_setup()
818 return -ENODEV; in mpc83xx_add_bridge()
825 return -ENOMEM; in mpc83xx_add_bridge()
853 bus_range = of_get_property(dev, "bus-range", &len); in mpc83xx_add_bridge()
855 printk(KERN_WARNING "Can't get bus-range for %pOF, assume" in mpc83xx_add_bridge()
862 return -ENOMEM; in mpc83xx_add_bridge()
864 hose->first_busno = bus_range ? bus_range[0] : 0; in mpc83xx_add_bridge()
865 hose->last_busno = bus_range ? bus_range[1] : 0xff; in mpc83xx_add_bridge()
867 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { in mpc83xx_add_bridge()
877 "Firmware bus number: %d->%d\n", in mpc83xx_add_bridge()
878 (unsigned long long)rsrc_reg.start, hose->first_busno, in mpc83xx_add_bridge()
879 hose->last_busno); in mpc83xx_add_bridge()
881 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", in mpc83xx_add_bridge()
882 hose, hose->cfg_addr, hose->cfg_data); in mpc83xx_add_bridge()
899 struct mpc83xx_pcie_priv *pcie = hose->dn->data; in fsl_pci_immrbar_base() local
904 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; in fsl_pci_immrbar_base()
923 pci_bus_read_config_dword(hose->bus, in fsl_pci_immrbar_base()
927 * For PEXCSRBAR, bit 3-0 indicate prefetchable and in fsl_pci_immrbar_base()
955 regs->gpr[rd] = 0xffffffff; in mcheck_handle_load()
959 regs->gpr[rd] = 0xffffffff; in mcheck_handle_load()
960 regs->gpr[ra] += regs->gpr[rb]; in mcheck_handle_load()
964 regs->gpr[rd] = 0xff; in mcheck_handle_load()
968 regs->gpr[rd] = 0xff; in mcheck_handle_load()
969 regs->gpr[ra] += regs->gpr[rb]; in mcheck_handle_load()
974 regs->gpr[rd] = 0xffff; in mcheck_handle_load()
978 regs->gpr[rd] = 0xffff; in mcheck_handle_load()
979 regs->gpr[ra] += regs->gpr[rb]; in mcheck_handle_load()
983 regs->gpr[rd] = ~0UL; in mcheck_handle_load()
987 regs->gpr[rd] = ~0UL; in mcheck_handle_load()
988 regs->gpr[ra] += regs->gpr[rb]; in mcheck_handle_load()
997 regs->gpr[rd] = 0xffffffff; in mcheck_handle_load()
1001 regs->gpr[rd] = 0xffffffff; in mcheck_handle_load()
1002 regs->gpr[ra] += (s16)d; in mcheck_handle_load()
1006 regs->gpr[rd] = 0xff; in mcheck_handle_load()
1010 regs->gpr[rd] = 0xff; in mcheck_handle_load()
1011 regs->gpr[ra] += (s16)d; in mcheck_handle_load()
1015 regs->gpr[rd] = 0xffff; in mcheck_handle_load()
1019 regs->gpr[rd] = 0xffff; in mcheck_handle_load()
1020 regs->gpr[ra] += (s16)d; in mcheck_handle_load()
1024 regs->gpr[rd] = ~0UL; in mcheck_handle_load()
1028 regs->gpr[rd] = ~0UL; in mcheck_handle_load()
1029 regs->gpr[ra] += (s16)d; in mcheck_handle_load()
1046 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)) in is_in_pci_mem_space()
1050 res = &hose->mem_resources[i]; in is_in_pci_mem_space()
1051 if ((res->flags & IORESOURCE_MEM) && in is_in_pci_mem_space()
1052 addr >= res->start && addr <= res->end) in is_in_pci_mem_space()
1066 if (regs->msr & MSR_GS) in fsl_pci_mcheck_exception()
1078 (void __user *)regs->nip, sizeof(inst)); in fsl_pci_mcheck_exception()
1080 ret = get_kernel_nofault(inst, (void *)regs->nip); in fsl_pci_mcheck_exception()
1083 regs->nip += 4; in fsl_pci_mcheck_exception()
1094 { .compatible = "fsl,mpc8540-pci", },
1095 { .compatible = "fsl,mpc8548-pcie", },
1096 { .compatible = "fsl,mpc8610-pci", },
1097 { .compatible = "fsl,mpc8641-pcie", },
1098 { .compatible = "fsl,qoriq-pcie", },
1099 { .compatible = "fsl,qoriq-pcie-v2.1", },
1100 { .compatible = "fsl,qoriq-pcie-v2.2", },
1101 { .compatible = "fsl,qoriq-pcie-v2.3", },
1102 { .compatible = "fsl,qoriq-pcie-v2.4", },
1103 { .compatible = "fsl,qoriq-pcie-v3.0", },
1109 { .compatible = "fsl,p1022-pcie", },
1110 { .compatible = "fsl,p4080-pcie", },
1138 * various bugs with primary-less systems are fixed. in fsl_pci_assign_primary()
1153 struct ccsr_pci __iomem *pci = hose->private_data; in fsl_pci_pme_handle()
1156 dr = in_be32(&pci->pex_pme_mes_dr); in fsl_pci_pme_handle()
1160 out_be32(&pci->pex_pme_mes_dr, dr); in fsl_pci_pme_handle()
1174 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list); in fsl_pci_pme_probe()
1177 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); in fsl_pci_pme_probe()
1179 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); in fsl_pci_pme_probe()
1181 pme_irq = irq_of_parse_and_map(hose->dn, 0); in fsl_pci_pme_probe()
1183 dev_err(&dev->dev, "Failed to map PME interrupt.\n"); in fsl_pci_pme_probe()
1185 return -ENXIO; in fsl_pci_pme_probe()
1188 res = devm_request_irq(hose->parent, pme_irq, in fsl_pci_pme_probe()
1193 dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq); in fsl_pci_pme_probe()
1196 return -ENODEV; in fsl_pci_pme_probe()
1199 pci = hose->private_data; in fsl_pci_pme_probe()
1202 clrbits32(&pci->pex_pme_mes_disr, in fsl_pci_pme_probe()
1205 out_be32(&pci->pex_pme_mes_ier, 0); in fsl_pci_pme_probe()
1206 setbits32(&pci->pex_pme_mes_ier, in fsl_pci_pme_probe()
1210 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); in fsl_pci_pme_probe()
1212 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); in fsl_pci_pme_probe()
1219 struct ccsr_pci __iomem *pci = hose->private_data; in send_pme_turnoff_message()
1224 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); in send_pme_turnoff_message()
1228 dr = in_be32(&pci->pex_pme_mes_dr); in send_pme_turnoff_message()
1230 out_be32(&pci->pex_pme_mes_dr, dr); in send_pme_turnoff_message()
1255 struct ccsr_pci __iomem *pci = hose->private_data; in fsl_pci_syscore_do_resume()
1260 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); in fsl_pci_syscore_do_resume()
1264 dr = in_be32(&pci->pex_pme_mes_dr); in fsl_pci_syscore_do_resume()
1266 out_be32(&pci->pex_pme_mes_dr, dr); in fsl_pci_syscore_do_resume()
1301 .of_node = pdev->dev.of_node in add_err_dev()
1304 errdev = platform_device_register_resndata(&pdev->dev, in add_err_dev()
1305 "mpc85xx-pci-edac", in add_err_dev()
1307 pdev->resource, in add_err_dev()
1308 pdev->num_resources, in add_err_dev()
1319 node = pdev->dev.of_node; in fsl_pci_probe()
1326 dev_err(&pdev->dev, "couldn't register error device: %d\n", in fsl_pci_probe()
1334 .name = "fsl-pci",