Lines Matching +full:0 +full:xc
44 #define DBG_VERBOSE(fmt...) do { } while(0)
78 * or 0 if there is no new entry.
87 return 0; in xive_read_eq()
92 return 0; in xive_read_eq()
100 if (q->idx == 0) in xive_read_eq()
104 return cur & 0x7fffffff; in xive_read_eq()
114 * (0xff if none) and return what was found (0 if none).
130 static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek) in xive_scan_interrupts() argument
132 u32 irq = 0; in xive_scan_interrupts()
133 u8 prio = 0; in xive_scan_interrupts()
136 while (xc->pending_prio != 0) { in xive_scan_interrupts()
139 prio = ffs(xc->pending_prio) - 1; in xive_scan_interrupts()
143 irq = xive_read_eq(&xc->queue[prio], just_peek); in xive_scan_interrupts()
161 xc->pending_prio &= ~(1 << prio); in xive_scan_interrupts()
168 q = &xc->queue[prio]; in xive_scan_interrupts()
170 int p = atomic_xchg(&q->pending_count, 0); in xive_scan_interrupts()
178 /* If nothing was found, set CPPR to 0xff */ in xive_scan_interrupts()
179 if (irq == 0) in xive_scan_interrupts()
180 prio = 0xff; in xive_scan_interrupts()
183 if (prio != xc->cppr) { in xive_scan_interrupts()
185 xc->cppr = prio; in xive_scan_interrupts()
208 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0); in xive_esb_read()
244 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); in xmon_xive_do_dump() local
247 if (xc) { in xmon_xive_do_dump()
248 xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr); in xmon_xive_do_dump()
252 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET); in xmon_xive_do_dump()
254 xmon_printf("IPI=0x%08x PQ=%c%c ", xc->hw_ipi, in xmon_xive_do_dump()
259 xive_dump_eq("EQ", &xc->queue[xive_irq_priority]); in xmon_xive_do_dump()
280 xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc); in xmon_xive_get_irq_config()
284 xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ", in xmon_xive_get_irq_config()
303 return 0; in xmon_xive_get_irq_config()
310 struct xive_cpu *xc = __this_cpu_read(xive_cpu); in xive_get_irq() local
327 xive_ops->update_pending(xc); in xive_get_irq()
329 DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio); in xive_get_irq()
332 irq = xive_scan_interrupts(xc, false); in xive_get_irq()
334 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n", in xive_get_irq()
335 irq, xc->pending_prio); in xive_get_irq()
339 return 0; in xive_get_irq()
353 static void xive_do_queue_eoi(struct xive_cpu *xc) in xive_do_queue_eoi() argument
355 if (xive_scan_interrupts(xc, true) != 0) { in xive_do_queue_eoi()
356 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio); in xive_do_queue_eoi()
370 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0); in xive_do_source_eoi()
376 * on P9 DD1.0 needed a latch to be clared in the LPC bridge in xive_do_source_eoi()
406 out_be64(xd->trig_mmio, 0); in xive_do_source_eoi()
415 struct xive_cpu *xc = __this_cpu_read(xive_cpu); in xive_irq_eoi() local
417 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n", in xive_irq_eoi()
418 d->irq, irqd_to_hwirq(d), xc->pending_prio); in xive_irq_eoi()
437 xive_do_queue_eoi(xc); in xive_irq_eoi()
479 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); in xive_try_pick_target() local
480 struct xive_q *q = &xc->queue[xive_irq_priority]; in xive_try_pick_target()
503 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); in xive_dec_target_count() local
504 struct xive_q *q = &xc->queue[xive_irq_priority]; in xive_dec_target_count()
506 if (WARN_ON(cpu < 0 || !xc)) { in xive_dec_target_count()
507 pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc); in xive_dec_target_count()
533 for (i = 0; i < first && cpu < nr_cpu_ids; i++) in xive_find_target_in_mask()
584 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); in xive_pick_irq_target() local
585 if (xc->chip_id == xd->src_chip) in xive_pick_irq_target()
594 if (cpu >= 0) in xive_pick_irq_target()
611 pr_devel("xive_irq_startup: irq %d [0x%x] data @%p\n", in xive_irq_startup()
654 return 0; in xive_irq_startup()
663 pr_devel("xive_irq_shutdown: irq %d [0x%x] data @%p\n", in xive_irq_shutdown()
678 0xff, XIVE_BAD_IRQ); in xive_irq_shutdown()
693 * be fixed by P9 DD2.0, if that is the case, firmware in xive_irq_unmask()
716 * be fixed by P9 DD2.0, if that is the case, firmware in xive_irq_mask()
723 0xff, d->irq); in xive_irq_mask()
737 int rc = 0; in xive_irq_set_affinity()
779 if (rc < 0) { in xive_irq_set_affinity()
784 pr_devel(" target: 0x%x\n", target); in xive_irq_set_affinity()
824 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n", in xive_irq_set_type()
839 return 0; in xive_irq_retrigger()
848 * Note: We pass "0" to the hw_irq argument in order to in xive_irq_retrigger()
853 xive_do_source_eoi(0, xd); in xive_irq_retrigger()
898 return 0; in xive_irq_set_vcpu_affinity()
937 return 0; in xive_irq_set_vcpu_affinity()
978 return 0; in xive_irq_set_vcpu_affinity()
1002 return 0; in xive_get_irqchip_state()
1072 return 0; in xive_irq_alloc_data()
1090 struct xive_cpu *xc; in xive_cause_ipi() local
1093 xc = per_cpu(xive_cpu, cpu); in xive_cause_ipi()
1095 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n", in xive_cause_ipi()
1096 smp_processor_id(), cpu, xc->hw_ipi); in xive_cause_ipi()
1098 xd = &xc->ipi_data; in xive_cause_ipi()
1101 out_be64(xd->trig_mmio, 0); in xive_cause_ipi()
1111 struct xive_cpu *xc = __this_cpu_read(xive_cpu); in xive_ipi_eoi() local
1114 if (!xc) in xive_ipi_eoi()
1117 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n", in xive_ipi_eoi()
1118 d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio); in xive_ipi_eoi()
1120 xive_do_source_eoi(xc->hw_ipi, &xc->ipi_data); in xive_ipi_eoi()
1121 xive_do_queue_eoi(xc); in xive_ipi_eoi()
1152 virq = irq_create_mapping(xive_irq_domain, 0); in xive_request_ipi()
1161 struct xive_cpu *xc; in xive_setup_cpu_ipi() local
1166 xc = per_cpu(xive_cpu, cpu); in xive_setup_cpu_ipi()
1169 if (xc->hw_ipi != XIVE_BAD_IRQ) in xive_setup_cpu_ipi()
1170 return 0; in xive_setup_cpu_ipi()
1172 /* Grab an IPI from the backend, this will populate xc->hw_ipi */ in xive_setup_cpu_ipi()
1173 if (xive_ops->get_ipi(cpu, xc)) in xive_setup_cpu_ipi()
1180 rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data); in xive_setup_cpu_ipi()
1185 rc = xive_ops->configure_irq(xc->hw_ipi, in xive_setup_cpu_ipi()
1193 xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio); in xive_setup_cpu_ipi()
1196 xive_do_source_set_mask(&xc->ipi_data, false); in xive_setup_cpu_ipi()
1198 return 0; in xive_setup_cpu_ipi()
1201 static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc) in xive_cleanup_cpu_ipi() argument
1206 if (xc->hw_ipi == XIVE_BAD_IRQ) in xive_cleanup_cpu_ipi()
1210 xive_do_source_set_mask(&xc->ipi_data, true); in xive_cleanup_cpu_ipi()
1219 xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(), in xive_cleanup_cpu_ipi()
1220 0xff, xive_ipi_irq); in xive_cleanup_cpu_ipi()
1223 xive_ops->put_ipi(cpu, xc); in xive_cleanup_cpu_ipi()
1251 /* IPIs are special and come up with HW number 0 */ in xive_irq_domain_map()
1252 if (hw == 0) { in xive_irq_domain_map()
1259 return 0; in xive_irq_domain_map()
1269 return 0; in xive_irq_domain_map()
1290 *out_hwirq = intspec[0]; in xive_irq_domain_xlate()
1304 return 0; in xive_irq_domain_xlate()
1329 static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc) in xive_cleanup_cpu_queues() argument
1331 if (xc->queue[xive_irq_priority].qpage) in xive_cleanup_cpu_queues()
1332 xive_ops->cleanup_queue(cpu, xc, xive_irq_priority); in xive_cleanup_cpu_queues()
1335 static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc) in xive_setup_cpu_queues() argument
1337 int rc = 0; in xive_setup_cpu_queues()
1340 if (!xc->queue[xive_irq_priority].qpage) in xive_setup_cpu_queues()
1341 rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority); in xive_setup_cpu_queues()
1348 struct xive_cpu *xc; in xive_prepare_cpu() local
1350 xc = per_cpu(xive_cpu, cpu); in xive_prepare_cpu()
1351 if (!xc) { in xive_prepare_cpu()
1354 xc = kzalloc_node(sizeof(struct xive_cpu), in xive_prepare_cpu()
1356 if (!xc) in xive_prepare_cpu()
1360 xc->chip_id = of_get_ibm_chip_id(np); in xive_prepare_cpu()
1362 xc->hw_ipi = XIVE_BAD_IRQ; in xive_prepare_cpu()
1364 per_cpu(xive_cpu, cpu) = xc; in xive_prepare_cpu()
1368 return xive_setup_cpu_queues(cpu, xc); in xive_prepare_cpu()
1373 struct xive_cpu *xc = __this_cpu_read(xive_cpu); in xive_setup_cpu() local
1377 xive_ops->setup_cpu(smp_processor_id(), xc); in xive_setup_cpu()
1379 /* Set CPPR to 0xff to enable flow of interrupts */ in xive_setup_cpu()
1380 xc->cppr = 0xff; in xive_setup_cpu()
1381 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); in xive_setup_cpu()
1409 static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc) in xive_flush_cpu_queue() argument
1417 while ((irq = xive_scan_interrupts(xc, false)) != 0) { in xive_flush_cpu_queue()
1431 if (d->domain != xive_irq_domain || hw_irq == 0) in xive_flush_cpu_queue()
1466 struct xive_cpu *xc = __this_cpu_read(xive_cpu); in xive_smp_disable_cpu() local
1472 /* Set CPPR to 0 to disable flow of interrupts */ in xive_smp_disable_cpu()
1473 xc->cppr = 0; in xive_smp_disable_cpu()
1474 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); in xive_smp_disable_cpu()
1477 xive_flush_cpu_queue(cpu, xc); in xive_smp_disable_cpu()
1480 xc->cppr = 0xff; in xive_smp_disable_cpu()
1481 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); in xive_smp_disable_cpu()
1486 struct xive_cpu *xc = __this_cpu_read(xive_cpu); in xive_flush_interrupt() local
1490 xive_flush_cpu_queue(cpu, xc); in xive_flush_interrupt()
1499 struct xive_cpu *xc = __this_cpu_read(xive_cpu); in xive_teardown_cpu() local
1502 /* Set CPPR to 0 to disable flow of interrupts */ in xive_teardown_cpu()
1503 xc->cppr = 0; in xive_teardown_cpu()
1504 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); in xive_teardown_cpu()
1507 xive_ops->teardown_cpu(cpu, xc); in xive_teardown_cpu()
1511 xive_cleanup_cpu_ipi(cpu, xc); in xive_teardown_cpu()
1515 xive_cleanup_cpu_queues(cpu, xc); in xive_teardown_cpu()
1563 memset(qpage, 0, 1 << queue_shift); in xive_queue_page_alloc()
1571 return 0; in xive_off()
1577 struct xive_cpu *xc = per_cpu(xive_cpu, cpu); in xive_debug_show_cpu() local
1580 if (xc) { in xive_debug_show_cpu()
1581 seq_printf(m, "pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr); in xive_debug_show_cpu()
1585 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET); in xive_debug_show_cpu()
1587 seq_printf(m, "IPI=0x%08x PQ=%c%c ", xc->hw_ipi, in xive_debug_show_cpu()
1593 struct xive_q *q = &xc->queue[xive_irq_priority]; in xive_debug_show_cpu()
1624 seq_printf(m, "IRQ 0x%08x : no config rc=%d\n", hw_irq, rc); in xive_debug_show_irq()
1628 seq_printf(m, "IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ", in xive_debug_show_irq()
1663 /* IPIs are special (HW number 0) */ in xive_core_debug_show()
1667 return 0; in xive_core_debug_show()
1676 return 0; in xive_core_debug_init()