Lines Matching full:apic
4 * Local APIC virtualization
78 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_pending_eoi() local
80 return apic_test_vector(vector, apic->regs + APIC_ISR) || in kvm_apic_pending_eoi()
81 apic_test_vector(vector, apic->regs + APIC_IRR); in kvm_apic_pending_eoi()
97 static inline int apic_enabled(struct kvm_lapic *apic) in apic_enabled() argument
99 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); in apic_enabled()
109 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic) in kvm_x2apic_id() argument
111 return apic->vcpu->vcpu_id; in kvm_x2apic_id()
199 * (if clean) or the APIC registers (if dirty). in kvm_recalculate_apic_map()
210 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); in kvm_recalculate_apic_map()
222 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_recalculate_apic_map() local
232 xapic_id = kvm_xapic_id(apic); in kvm_recalculate_apic_map()
233 x2apic_id = kvm_x2apic_id(apic); in kvm_recalculate_apic_map()
236 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) && in kvm_recalculate_apic_map()
238 new->phys_map[x2apic_id] = apic; in kvm_recalculate_apic_map()
240 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around, in kvm_recalculate_apic_map()
241 * prevent them from masking VCPUs with APIC ID <= 0xff. in kvm_recalculate_apic_map()
243 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) in kvm_recalculate_apic_map()
244 new->phys_map[xapic_id] = apic; in kvm_recalculate_apic_map()
246 if (!kvm_apic_sw_enabled(apic)) in kvm_recalculate_apic_map()
249 ldr = kvm_lapic_get_reg(apic, APIC_LDR); in kvm_recalculate_apic_map()
251 if (apic_x2apic_mode(apic)) { in kvm_recalculate_apic_map()
255 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) in kvm_recalculate_apic_map()
265 cluster[ffs(mask) - 1] = apic; in kvm_recalculate_apic_map()
272 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty. in kvm_recalculate_apic_map()
285 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) in apic_set_spiv() argument
289 kvm_lapic_set_reg(apic, APIC_SPIV, val); in apic_set_spiv()
291 if (enabled != apic->sw_enabled) { in apic_set_spiv()
292 apic->sw_enabled = enabled; in apic_set_spiv()
298 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in apic_set_spiv()
303 kvm_make_request(KVM_REQ_APF_READY, apic->vcpu); in apic_set_spiv()
306 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id) in kvm_apic_set_xapic_id() argument
308 kvm_lapic_set_reg(apic, APIC_ID, id << 24); in kvm_apic_set_xapic_id()
309 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_xapic_id()
312 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) in kvm_apic_set_ldr() argument
314 kvm_lapic_set_reg(apic, APIC_LDR, id); in kvm_apic_set_ldr()
315 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_ldr()
318 static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val) in kvm_apic_set_dfr() argument
320 kvm_lapic_set_reg(apic, APIC_DFR, val); in kvm_apic_set_dfr()
321 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_dfr()
329 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id) in kvm_apic_set_x2apic_id() argument
333 WARN_ON_ONCE(id != apic->vcpu->vcpu_id); in kvm_apic_set_x2apic_id()
335 kvm_lapic_set_reg(apic, APIC_ID, id); in kvm_apic_set_x2apic_id()
336 kvm_lapic_set_reg(apic, APIC_LDR, ldr); in kvm_apic_set_x2apic_id()
337 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_x2apic_id()
340 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) in apic_lvt_enabled() argument
342 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); in apic_lvt_enabled()
345 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) in apic_lvtt_oneshot() argument
347 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; in apic_lvtt_oneshot()
350 static inline int apic_lvtt_period(struct kvm_lapic *apic) in apic_lvtt_period() argument
352 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; in apic_lvtt_period()
355 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) in apic_lvtt_tscdeadline() argument
357 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; in apic_lvtt_tscdeadline()
367 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_version() local
383 kvm_lapic_set_reg(apic, APIC_LVR, v); in kvm_apic_set_version()
455 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_irr() local
457 return __kvm_apic_update_irr(pir, apic->regs, max_irr); in kvm_apic_update_irr()
461 static inline int apic_search_irr(struct kvm_lapic *apic) in apic_search_irr() argument
463 return find_highest_vector(apic->regs + APIC_IRR); in apic_search_irr()
466 static inline int apic_find_highest_irr(struct kvm_lapic *apic) in apic_find_highest_irr() argument
474 if (!apic->irr_pending) in apic_find_highest_irr()
477 result = apic_search_irr(apic); in apic_find_highest_irr()
483 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) in apic_clear_irr() argument
487 vcpu = apic->vcpu; in apic_clear_irr()
491 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
493 apic_find_highest_irr(apic)); in apic_clear_irr()
495 apic->irr_pending = false; in apic_clear_irr()
496 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
497 if (apic_search_irr(apic) != -1) in apic_clear_irr()
498 apic->irr_pending = true; in apic_clear_irr()
504 apic_clear_irr(vec, vcpu->arch.apic); in kvm_apic_clear_irr()
508 static inline void apic_set_isr(int vec, struct kvm_lapic *apic) in apic_set_isr() argument
512 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) in apic_set_isr()
515 vcpu = apic->vcpu; in apic_set_isr()
518 * With APIC virtualization enabled, all caching is disabled in apic_set_isr()
525 ++apic->isr_count; in apic_set_isr()
526 BUG_ON(apic->isr_count > MAX_APIC_VECTOR); in apic_set_isr()
532 apic->highest_isr_cache = vec; in apic_set_isr()
536 static inline int apic_find_highest_isr(struct kvm_lapic *apic) in apic_find_highest_isr() argument
542 * is always -1, with APIC virtualization enabled. in apic_find_highest_isr()
544 if (!apic->isr_count) in apic_find_highest_isr()
546 if (likely(apic->highest_isr_cache != -1)) in apic_find_highest_isr()
547 return apic->highest_isr_cache; in apic_find_highest_isr()
549 result = find_highest_vector(apic->regs + APIC_ISR); in apic_find_highest_isr()
555 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) in apic_clear_isr() argument
558 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) in apic_clear_isr()
561 vcpu = apic->vcpu; in apic_clear_isr()
564 * We do get here for APIC virtualization enabled if the guest in apic_clear_isr()
565 * uses the Hyper-V APIC enlightenment. In this case we may need in apic_clear_isr()
572 apic_find_highest_isr(apic)); in apic_clear_isr()
574 --apic->isr_count; in apic_clear_isr()
575 BUG_ON(apic->isr_count < 0); in apic_clear_isr()
576 apic->highest_isr_cache = -1; in apic_clear_isr()
587 return apic_find_highest_irr(vcpu->arch.apic); in kvm_lapic_find_highest_irr()
591 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
598 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_irq() local
600 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, in kvm_apic_set_irq()
705 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr) in apic_has_interrupt_for_ppr() argument
708 if (apic->vcpu->arch.apicv_active) in apic_has_interrupt_for_ppr()
709 highest_irr = kvm_x86_ops.sync_pir_to_irr(apic->vcpu); in apic_has_interrupt_for_ppr()
711 highest_irr = apic_find_highest_irr(apic); in apic_has_interrupt_for_ppr()
717 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr) in __apic_update_ppr() argument
722 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); in __apic_update_ppr()
723 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); in __apic_update_ppr()
724 isr = apic_find_highest_isr(apic); in __apic_update_ppr()
734 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); in __apic_update_ppr()
739 static void apic_update_ppr(struct kvm_lapic *apic) in apic_update_ppr() argument
743 if (__apic_update_ppr(apic, &ppr) && in apic_update_ppr()
744 apic_has_interrupt_for_ppr(apic, ppr) != -1) in apic_update_ppr()
745 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_update_ppr()
750 apic_update_ppr(vcpu->arch.apic); in kvm_apic_update_ppr()
754 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) in apic_set_tpr() argument
756 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); in apic_set_tpr()
757 apic_update_ppr(apic); in apic_set_tpr()
760 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) in kvm_apic_broadcast() argument
762 return mda == (apic_x2apic_mode(apic) ? in kvm_apic_broadcast()
766 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) in kvm_apic_match_physical_addr() argument
768 if (kvm_apic_broadcast(apic, mda)) in kvm_apic_match_physical_addr()
771 if (apic_x2apic_mode(apic)) in kvm_apic_match_physical_addr()
772 return mda == kvm_x2apic_id(apic); in kvm_apic_match_physical_addr()
777 * this allows unique addressing of VCPUs with APIC ID over 0xff. in kvm_apic_match_physical_addr()
780 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic)) in kvm_apic_match_physical_addr()
783 return mda == kvm_xapic_id(apic); in kvm_apic_match_physical_addr()
786 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) in kvm_apic_match_logical_addr() argument
790 if (kvm_apic_broadcast(apic, mda)) in kvm_apic_match_logical_addr()
793 logical_id = kvm_lapic_get_reg(apic, APIC_LDR); in kvm_apic_match_logical_addr()
795 if (apic_x2apic_mode(apic)) in kvm_apic_match_logical_addr()
801 switch (kvm_lapic_get_reg(apic, APIC_DFR)) { in kvm_apic_match_logical_addr()
812 /* The KVM local APIC implementation has two quirks:
843 struct kvm_lapic *target = vcpu->arch.apic; in kvm_apic_match_dest()
1065 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, in __apic_accept_irq() argument
1070 struct kvm_vcpu *vcpu = apic->vcpu; in __apic_accept_irq()
1083 if (unlikely(!apic_enabled(apic))) in __apic_accept_irq()
1093 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { in __apic_accept_irq()
1096 apic->regs + APIC_TMR); in __apic_accept_irq()
1099 apic->regs + APIC_TMR); in __apic_accept_irq()
1103 kvm_lapic_set_irr(vector, apic); in __apic_accept_irq()
1132 apic->pending_events = (1UL << KVM_APIC_INIT); in __apic_accept_irq()
1140 apic->sipi_vector = vector; in __apic_accept_irq()
1143 set_bit(KVM_APIC_SIPI, &apic->pending_events); in __apic_accept_irq()
1213 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) in kvm_ioapic_handles_vector() argument
1215 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); in kvm_ioapic_handles_vector()
1218 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) in kvm_ioapic_send_eoi() argument
1223 if (!kvm_ioapic_handles_vector(apic, vector)) in kvm_ioapic_send_eoi()
1227 if (irqchip_split(apic->vcpu->kvm)) { in kvm_ioapic_send_eoi()
1228 apic->vcpu->arch.pending_ioapic_eoi = vector; in kvm_ioapic_send_eoi()
1229 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); in kvm_ioapic_send_eoi()
1233 if (apic_test_vector(vector, apic->regs + APIC_TMR)) in kvm_ioapic_send_eoi()
1238 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); in kvm_ioapic_send_eoi()
1241 static int apic_set_eoi(struct kvm_lapic *apic) in apic_set_eoi() argument
1243 int vector = apic_find_highest_isr(apic); in apic_set_eoi()
1245 trace_kvm_eoi(apic, vector); in apic_set_eoi()
1254 apic_clear_isr(vector, apic); in apic_set_eoi()
1255 apic_update_ppr(apic); in apic_set_eoi()
1257 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap)) in apic_set_eoi()
1258 kvm_hv_synic_send_eoi(apic->vcpu, vector); in apic_set_eoi()
1260 kvm_ioapic_send_eoi(apic, vector); in apic_set_eoi()
1261 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_set_eoi()
1271 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_eoi_accelerated() local
1273 trace_kvm_eoi(apic, vector); in kvm_apic_set_eoi_accelerated()
1275 kvm_ioapic_send_eoi(apic, vector); in kvm_apic_set_eoi_accelerated()
1276 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in kvm_apic_set_eoi_accelerated()
1280 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high) in kvm_apic_send_ipi() argument
1291 if (apic_x2apic_mode(apic)) in kvm_apic_send_ipi()
1298 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); in kvm_apic_send_ipi()
1301 static u32 apic_get_tmcct(struct kvm_lapic *apic) in apic_get_tmcct() argument
1307 ASSERT(apic != NULL); in apic_get_tmcct()
1310 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || in apic_get_tmcct()
1311 apic->lapic_timer.period == 0) in apic_get_tmcct()
1315 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in apic_get_tmcct()
1319 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); in apic_get_tmcct()
1321 (APIC_BUS_CYCLE_NS * apic->divide_count)); in apic_get_tmcct()
1326 static void __report_tpr_access(struct kvm_lapic *apic, bool write) in __report_tpr_access() argument
1328 struct kvm_vcpu *vcpu = apic->vcpu; in __report_tpr_access()
1336 static inline void report_tpr_access(struct kvm_lapic *apic, bool write) in report_tpr_access() argument
1338 if (apic->vcpu->arch.tpr_access_reporting) in report_tpr_access()
1339 __report_tpr_access(apic, write); in report_tpr_access()
1342 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) in __apic_read() argument
1354 if (apic_lvtt_tscdeadline(apic)) in __apic_read()
1357 val = apic_get_tmcct(apic); in __apic_read()
1360 apic_update_ppr(apic); in __apic_read()
1361 val = kvm_lapic_get_reg(apic, offset); in __apic_read()
1364 report_tpr_access(apic, false); in __apic_read()
1367 val = kvm_lapic_get_reg(apic, offset); in __apic_read()
1383 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, in kvm_lapic_reg_read() argument
1414 if (!apic_x2apic_mode(apic)) in kvm_lapic_reg_read()
1423 result = __apic_read(apic, offset & ~0xf); in kvm_lapic_reg_read()
1434 printk(KERN_ERR "Local APIC read with len = %x, " in kvm_lapic_reg_read()
1442 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) in apic_mmio_in_range() argument
1444 return addr >= apic->base_address && in apic_mmio_in_range()
1445 addr < apic->base_address + LAPIC_MMIO_LENGTH; in apic_mmio_in_range()
1451 struct kvm_lapic *apic = to_lapic(this); in apic_mmio_read() local
1452 u32 offset = address - apic->base_address; in apic_mmio_read()
1454 if (!apic_mmio_in_range(apic, address)) in apic_mmio_read()
1457 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { in apic_mmio_read()
1466 kvm_lapic_reg_read(apic, offset, len, data); in apic_mmio_read()
1471 static void update_divide_count(struct kvm_lapic *apic) in update_divide_count() argument
1475 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); in update_divide_count()
1478 apic->divide_count = 0x1 << (tmp2 & 0x7); in update_divide_count()
1481 static void limit_periodic_timer_frequency(struct kvm_lapic *apic) in limit_periodic_timer_frequency() argument
1488 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in limit_periodic_timer_frequency()
1491 if (apic->lapic_timer.period < min_period) { in limit_periodic_timer_frequency()
1495 apic->vcpu->vcpu_id, in limit_periodic_timer_frequency()
1496 apic->lapic_timer.period, min_period); in limit_periodic_timer_frequency()
1497 apic->lapic_timer.period = min_period; in limit_periodic_timer_frequency()
1502 static void cancel_hv_timer(struct kvm_lapic *apic);
1504 static void apic_update_lvtt(struct kvm_lapic *apic) in apic_update_lvtt() argument
1506 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & in apic_update_lvtt()
1507 apic->lapic_timer.timer_mode_mask; in apic_update_lvtt()
1509 if (apic->lapic_timer.timer_mode != timer_mode) { in apic_update_lvtt()
1510 if (apic_lvtt_tscdeadline(apic) != (timer_mode == in apic_update_lvtt()
1512 hrtimer_cancel(&apic->lapic_timer.timer); in apic_update_lvtt()
1514 if (apic->lapic_timer.hv_timer_in_use) in apic_update_lvtt()
1515 cancel_hv_timer(apic); in apic_update_lvtt()
1517 kvm_lapic_set_reg(apic, APIC_TMICT, 0); in apic_update_lvtt()
1518 apic->lapic_timer.period = 0; in apic_update_lvtt()
1519 apic->lapic_timer.tscdeadline = 0; in apic_update_lvtt()
1521 apic->lapic_timer.timer_mode = timer_mode; in apic_update_lvtt()
1522 limit_periodic_timer_frequency(apic); in apic_update_lvtt()
1533 struct kvm_lapic *apic = vcpu->arch.apic; in lapic_timer_int_injected() local
1534 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); in lapic_timer_int_injected()
1536 if (kvm_apic_hw_enabled(apic)) { in lapic_timer_int_injected()
1538 void *bitmap = apic->regs + APIC_ISR; in lapic_timer_int_injected()
1541 bitmap = apic->regs + APIC_IRR; in lapic_timer_int_injected()
1551 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns; in __wait_lapic_expire()
1572 struct kvm_lapic *apic = vcpu->arch.apic; in adjust_lapic_timer_advance() local
1573 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns; in adjust_lapic_timer_advance()
1595 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in adjust_lapic_timer_advance()
1600 struct kvm_lapic *apic = vcpu->arch.apic; in __kvm_wait_lapic_expire() local
1603 tsc_deadline = apic->lapic_timer.expired_tscdeadline; in __kvm_wait_lapic_expire()
1604 apic->lapic_timer.expired_tscdeadline = 0; in __kvm_wait_lapic_expire()
1606 apic->lapic_timer.advance_expire_delta = guest_tsc - tsc_deadline; in __kvm_wait_lapic_expire()
1612 adjust_lapic_timer_advance(vcpu, apic->lapic_timer.advance_expire_delta); in __kvm_wait_lapic_expire()
1618 vcpu->arch.apic->lapic_timer.expired_tscdeadline && in kvm_wait_lapic_expire()
1619 vcpu->arch.apic->lapic_timer.timer_advance_ns && in kvm_wait_lapic_expire()
1625 static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic) in kvm_apic_inject_pending_timer_irqs() argument
1627 struct kvm_timer *ktimer = &apic->lapic_timer; in kvm_apic_inject_pending_timer_irqs()
1629 kvm_apic_local_deliver(apic, APIC_LVTT); in kvm_apic_inject_pending_timer_irqs()
1630 if (apic_lvtt_tscdeadline(apic)) { in kvm_apic_inject_pending_timer_irqs()
1632 } else if (apic_lvtt_oneshot(apic)) { in kvm_apic_inject_pending_timer_irqs()
1638 static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn) in apic_timer_expired() argument
1640 struct kvm_vcpu *vcpu = apic->vcpu; in apic_timer_expired()
1641 struct kvm_timer *ktimer = &apic->lapic_timer; in apic_timer_expired()
1643 if (atomic_read(&apic->lapic_timer.pending)) in apic_timer_expired()
1646 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use) in apic_timer_expired()
1651 kvm_apic_inject_pending_timer_irqs(apic); in apic_timer_expired()
1655 if (kvm_use_posted_timer_interrupt(apic->vcpu)) { in apic_timer_expired()
1663 if (vcpu->arch.apic->lapic_timer.expired_tscdeadline && in apic_timer_expired()
1664 vcpu->arch.apic->lapic_timer.timer_advance_ns) in apic_timer_expired()
1666 kvm_apic_inject_pending_timer_irqs(apic); in apic_timer_expired()
1670 atomic_inc(&apic->lapic_timer.pending); in apic_timer_expired()
1676 static void start_sw_tscdeadline(struct kvm_lapic *apic) in start_sw_tscdeadline() argument
1678 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_tscdeadline()
1682 struct kvm_vcpu *vcpu = apic->vcpu; in start_sw_tscdeadline()
1699 likely(ns > apic->lapic_timer.timer_advance_ns)) { in start_sw_tscdeadline()
1704 apic_timer_expired(apic, false); in start_sw_tscdeadline()
1709 static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict) in tmict_to_ns() argument
1711 return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count; in tmict_to_ns()
1714 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) in update_target_expiration() argument
1719 apic->lapic_timer.period = in update_target_expiration()
1720 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT)); in update_target_expiration()
1721 limit_periodic_timer_frequency(apic); in update_target_expiration()
1724 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in update_target_expiration()
1730 apic->divide_count, old_divisor); in update_target_expiration()
1732 apic->lapic_timer.tscdeadline += in update_target_expiration()
1733 nsec_to_cycles(apic->vcpu, ns_remaining_new) - in update_target_expiration()
1734 nsec_to_cycles(apic->vcpu, ns_remaining_old); in update_target_expiration()
1735 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); in update_target_expiration()
1738 static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg) in set_target_expiration() argument
1745 apic->lapic_timer.period = in set_target_expiration()
1746 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT)); in set_target_expiration()
1748 if (!apic->lapic_timer.period) { in set_target_expiration()
1749 apic->lapic_timer.tscdeadline = 0; in set_target_expiration()
1753 limit_periodic_timer_frequency(apic); in set_target_expiration()
1754 deadline = apic->lapic_timer.period; in set_target_expiration()
1756 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { in set_target_expiration()
1758 deadline = tmict_to_ns(apic, in set_target_expiration()
1759 kvm_lapic_get_reg(apic, count_reg)); in set_target_expiration()
1761 deadline = apic->lapic_timer.period; in set_target_expiration()
1762 else if (unlikely(deadline > apic->lapic_timer.period)) { in set_target_expiration()
1767 apic->vcpu->vcpu_id, in set_target_expiration()
1769 kvm_lapic_get_reg(apic, count_reg), in set_target_expiration()
1770 deadline, apic->lapic_timer.period); in set_target_expiration()
1771 kvm_lapic_set_reg(apic, count_reg, 0); in set_target_expiration()
1772 deadline = apic->lapic_timer.period; in set_target_expiration()
1777 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in set_target_expiration()
1778 nsec_to_cycles(apic->vcpu, deadline); in set_target_expiration()
1779 apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline); in set_target_expiration()
1784 static void advance_periodic_target_expiration(struct kvm_lapic *apic) in advance_periodic_target_expiration() argument
1797 apic->lapic_timer.target_expiration = in advance_periodic_target_expiration()
1798 ktime_add_ns(apic->lapic_timer.target_expiration, in advance_periodic_target_expiration()
1799 apic->lapic_timer.period); in advance_periodic_target_expiration()
1800 delta = ktime_sub(apic->lapic_timer.target_expiration, now); in advance_periodic_target_expiration()
1801 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in advance_periodic_target_expiration()
1802 nsec_to_cycles(apic->vcpu, delta); in advance_periodic_target_expiration()
1805 static void start_sw_period(struct kvm_lapic *apic) in start_sw_period() argument
1807 if (!apic->lapic_timer.period) in start_sw_period()
1811 apic->lapic_timer.target_expiration)) { in start_sw_period()
1812 apic_timer_expired(apic, false); in start_sw_period()
1814 if (apic_lvtt_oneshot(apic)) in start_sw_period()
1817 advance_periodic_target_expiration(apic); in start_sw_period()
1820 hrtimer_start(&apic->lapic_timer.timer, in start_sw_period()
1821 apic->lapic_timer.target_expiration, in start_sw_period()
1830 return vcpu->arch.apic->lapic_timer.hv_timer_in_use; in kvm_lapic_hv_timer_in_use()
1834 static void cancel_hv_timer(struct kvm_lapic *apic) in cancel_hv_timer() argument
1837 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in cancel_hv_timer()
1838 kvm_x86_ops.cancel_hv_timer(apic->vcpu); in cancel_hv_timer()
1839 apic->lapic_timer.hv_timer_in_use = false; in cancel_hv_timer()
1842 static bool start_hv_timer(struct kvm_lapic *apic) in start_hv_timer() argument
1844 struct kvm_timer *ktimer = &apic->lapic_timer; in start_hv_timer()
1845 struct kvm_vcpu *vcpu = apic->vcpu; in start_hv_timer()
1866 if (!apic_lvtt_period(apic)) { in start_hv_timer()
1872 cancel_hv_timer(apic); in start_hv_timer()
1874 apic_timer_expired(apic, false); in start_hv_timer()
1875 cancel_hv_timer(apic); in start_hv_timer()
1884 static void start_sw_timer(struct kvm_lapic *apic) in start_sw_timer() argument
1886 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_timer()
1889 if (apic->lapic_timer.hv_timer_in_use) in start_sw_timer()
1890 cancel_hv_timer(apic); in start_sw_timer()
1891 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) in start_sw_timer()
1894 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) in start_sw_timer()
1895 start_sw_period(apic); in start_sw_timer()
1896 else if (apic_lvtt_tscdeadline(apic)) in start_sw_timer()
1897 start_sw_tscdeadline(apic); in start_sw_timer()
1898 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); in start_sw_timer()
1901 static void restart_apic_timer(struct kvm_lapic *apic) in restart_apic_timer() argument
1905 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending)) in restart_apic_timer()
1908 if (!start_hv_timer(apic)) in restart_apic_timer()
1909 start_sw_timer(apic); in restart_apic_timer()
1916 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_expired_hv_timer() local
1920 if (!apic->lapic_timer.hv_timer_in_use) in kvm_lapic_expired_hv_timer()
1923 apic_timer_expired(apic, false); in kvm_lapic_expired_hv_timer()
1924 cancel_hv_timer(apic); in kvm_lapic_expired_hv_timer()
1926 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in kvm_lapic_expired_hv_timer()
1927 advance_periodic_target_expiration(apic); in kvm_lapic_expired_hv_timer()
1928 restart_apic_timer(apic); in kvm_lapic_expired_hv_timer()
1937 restart_apic_timer(vcpu->arch.apic); in kvm_lapic_switch_to_hv_timer()
1943 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_switch_to_sw_timer() local
1947 if (apic->lapic_timer.hv_timer_in_use) in kvm_lapic_switch_to_sw_timer()
1948 start_sw_timer(apic); in kvm_lapic_switch_to_sw_timer()
1955 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_restart_hv_timer() local
1957 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in kvm_lapic_restart_hv_timer()
1958 restart_apic_timer(apic); in kvm_lapic_restart_hv_timer()
1961 static void __start_apic_timer(struct kvm_lapic *apic, u32 count_reg) in __start_apic_timer() argument
1963 atomic_set(&apic->lapic_timer.pending, 0); in __start_apic_timer()
1965 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) in __start_apic_timer()
1966 && !set_target_expiration(apic, count_reg)) in __start_apic_timer()
1969 restart_apic_timer(apic); in __start_apic_timer()
1972 static void start_apic_timer(struct kvm_lapic *apic) in start_apic_timer() argument
1974 __start_apic_timer(apic, APIC_TMICT); in start_apic_timer()
1977 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) in apic_manage_nmi_watchdog() argument
1981 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { in apic_manage_nmi_watchdog()
1982 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; in apic_manage_nmi_watchdog()
1984 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
1986 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
1990 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) in kvm_lapic_reg_write() argument
1997 case APIC_ID: /* Local APIC ID */ in kvm_lapic_reg_write()
1998 if (!apic_x2apic_mode(apic)) in kvm_lapic_reg_write()
1999 kvm_apic_set_xapic_id(apic, val >> 24); in kvm_lapic_reg_write()
2005 report_tpr_access(apic, true); in kvm_lapic_reg_write()
2006 apic_set_tpr(apic, val & 0xff); in kvm_lapic_reg_write()
2010 apic_set_eoi(apic); in kvm_lapic_reg_write()
2014 if (!apic_x2apic_mode(apic)) in kvm_lapic_reg_write()
2015 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); in kvm_lapic_reg_write()
2021 if (!apic_x2apic_mode(apic)) in kvm_lapic_reg_write()
2022 kvm_apic_set_dfr(apic, val | 0x0FFFFFFF); in kvm_lapic_reg_write()
2029 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) in kvm_lapic_reg_write()
2031 apic_set_spiv(apic, val & mask); in kvm_lapic_reg_write()
2037 lvt_val = kvm_lapic_get_reg(apic, in kvm_lapic_reg_write()
2039 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, in kvm_lapic_reg_write()
2042 apic_update_lvtt(apic); in kvm_lapic_reg_write()
2043 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reg_write()
2051 kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2)); in kvm_lapic_reg_write()
2052 kvm_lapic_set_reg(apic, APIC_ICR, val); in kvm_lapic_reg_write()
2056 if (!apic_x2apic_mode(apic)) in kvm_lapic_reg_write()
2058 kvm_lapic_set_reg(apic, APIC_ICR2, val); in kvm_lapic_reg_write()
2062 apic_manage_nmi_watchdog(apic, val); in kvm_lapic_reg_write()
2072 if (!kvm_apic_sw_enabled(apic)) in kvm_lapic_reg_write()
2078 kvm_lapic_set_reg(apic, reg, val); in kvm_lapic_reg_write()
2083 if (!kvm_apic_sw_enabled(apic)) in kvm_lapic_reg_write()
2085 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); in kvm_lapic_reg_write()
2086 kvm_lapic_set_reg(apic, APIC_LVTT, val); in kvm_lapic_reg_write()
2087 apic_update_lvtt(apic); in kvm_lapic_reg_write()
2091 if (apic_lvtt_tscdeadline(apic)) in kvm_lapic_reg_write()
2094 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reg_write()
2095 kvm_lapic_set_reg(apic, APIC_TMICT, val); in kvm_lapic_reg_write()
2096 start_apic_timer(apic); in kvm_lapic_reg_write()
2100 uint32_t old_divisor = apic->divide_count; in kvm_lapic_reg_write()
2102 kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); in kvm_lapic_reg_write()
2103 update_divide_count(apic); in kvm_lapic_reg_write()
2104 if (apic->divide_count != old_divisor && in kvm_lapic_reg_write()
2105 apic->lapic_timer.period) { in kvm_lapic_reg_write()
2106 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reg_write()
2107 update_target_expiration(apic, old_divisor); in kvm_lapic_reg_write()
2108 restart_apic_timer(apic); in kvm_lapic_reg_write()
2113 if (apic_x2apic_mode(apic) && val != 0) in kvm_lapic_reg_write()
2122 if (!apic_x2apic_mode(apic) || (val & ~APIC_VECTOR_MASK)) in kvm_lapic_reg_write()
2125 kvm_apic_send_ipi(apic, APIC_DEST_SELF | val, 0); in kvm_lapic_reg_write()
2132 kvm_recalculate_apic_map(apic->vcpu->kvm); in kvm_lapic_reg_write()
2141 struct kvm_lapic *apic = to_lapic(this); in apic_mmio_write() local
2142 unsigned int offset = address - apic->base_address; in apic_mmio_write()
2145 if (!apic_mmio_in_range(apic, address)) in apic_mmio_write()
2148 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { in apic_mmio_write()
2157 * APIC register must be aligned on 128-bits boundary. in apic_mmio_write()
2166 kvm_lapic_reg_write(apic, offset & 0xff0, val); in apic_mmio_write()
2173 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); in kvm_lapic_set_eoi()
2177 /* emulate APIC access in a trap manner */
2185 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); in kvm_apic_write_nodecode()
2188 kvm_lapic_reg_write(vcpu->arch.apic, offset, val); in kvm_apic_write_nodecode()
2194 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_free_lapic() local
2196 if (!vcpu->arch.apic) in kvm_free_lapic()
2199 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_free_lapic()
2204 if (!apic->sw_enabled) in kvm_free_lapic()
2207 if (apic->regs) in kvm_free_lapic()
2208 free_page((unsigned long)apic->regs); in kvm_free_lapic()
2210 kfree(apic); in kvm_free_lapic()
2220 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_lapic_tscdeadline_msr() local
2222 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic)) in kvm_get_lapic_tscdeadline_msr()
2225 return apic->lapic_timer.tscdeadline; in kvm_get_lapic_tscdeadline_msr()
2230 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_set_lapic_tscdeadline_msr() local
2232 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic)) in kvm_set_lapic_tscdeadline_msr()
2235 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_set_lapic_tscdeadline_msr()
2236 apic->lapic_timer.tscdeadline = data; in kvm_set_lapic_tscdeadline_msr()
2237 start_apic_timer(apic); in kvm_set_lapic_tscdeadline_msr()
2242 apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4); in kvm_lapic_set_tpr()
2249 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); in kvm_lapic_get_cr8()
2257 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_set_base() local
2259 if (!apic) in kvm_lapic_set_base()
2267 if (!apic) in kvm_lapic_set_base()
2273 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2279 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_lapic_set_base()
2284 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2289 apic->base_address = apic->vcpu->arch.apic_base & in kvm_lapic_set_base()
2293 apic->base_address != APIC_DEFAULT_PHYS_BASE) in kvm_lapic_set_base()
2294 pr_warn_once("APIC base relocation is unsupported by KVM"); in kvm_lapic_set_base()
2299 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_apicv() local
2303 apic->irr_pending = true; in kvm_apic_update_apicv()
2304 apic->isr_count = 1; in kvm_apic_update_apicv()
2306 apic->irr_pending = (apic_search_irr(apic) != -1); in kvm_apic_update_apicv()
2307 apic->isr_count = count_vectors(apic->regs + APIC_ISR); in kvm_apic_update_apicv()
2314 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_reset() local
2317 if (!apic) in kvm_lapic_reset()
2320 /* Stop the timer in case it's a reset to an active apic */ in kvm_lapic_reset()
2321 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reset()
2326 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_reset()
2328 kvm_apic_set_version(apic->vcpu); in kvm_lapic_reset()
2331 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); in kvm_lapic_reset()
2332 apic_update_lvtt(apic); in kvm_lapic_reset()
2335 kvm_lapic_set_reg(apic, APIC_LVT0, in kvm_lapic_reset()
2337 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); in kvm_lapic_reset()
2339 kvm_apic_set_dfr(apic, 0xffffffffU); in kvm_lapic_reset()
2340 apic_set_spiv(apic, 0xff); in kvm_lapic_reset()
2341 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); in kvm_lapic_reset()
2342 if (!apic_x2apic_mode(apic)) in kvm_lapic_reset()
2343 kvm_apic_set_ldr(apic, 0); in kvm_lapic_reset()
2344 kvm_lapic_set_reg(apic, APIC_ESR, 0); in kvm_lapic_reset()
2345 kvm_lapic_set_reg(apic, APIC_ICR, 0); in kvm_lapic_reset()
2346 kvm_lapic_set_reg(apic, APIC_ICR2, 0); in kvm_lapic_reset()
2347 kvm_lapic_set_reg(apic, APIC_TDCR, 0); in kvm_lapic_reset()
2348 kvm_lapic_set_reg(apic, APIC_TMICT, 0); in kvm_lapic_reset()
2350 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); in kvm_lapic_reset()
2351 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); in kvm_lapic_reset()
2352 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); in kvm_lapic_reset()
2355 apic->highest_isr_cache = -1; in kvm_lapic_reset()
2356 update_divide_count(apic); in kvm_lapic_reset()
2357 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reset()
2362 apic_update_ppr(apic); in kvm_lapic_reset()
2381 static bool lapic_is_periodic(struct kvm_lapic *apic) in lapic_is_periodic() argument
2383 return apic_lvtt_period(apic); in lapic_is_periodic()
2388 struct kvm_lapic *apic = vcpu->arch.apic; in apic_has_pending_timer() local
2390 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) in apic_has_pending_timer()
2391 return atomic_read(&apic->lapic_timer.pending); in apic_has_pending_timer()
2396 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) in kvm_apic_local_deliver() argument
2398 u32 reg = kvm_lapic_get_reg(apic, lvt_type); in kvm_apic_local_deliver()
2402 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { in kvm_apic_local_deliver()
2407 r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL); in kvm_apic_local_deliver()
2409 kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED); in kvm_apic_local_deliver()
2417 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_nmi_wd_deliver() local
2419 if (apic) in kvm_apic_nmi_wd_deliver()
2420 kvm_apic_local_deliver(apic, APIC_LVT0); in kvm_apic_nmi_wd_deliver()
2431 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); in apic_timer_fn() local
2433 apic_timer_expired(apic, true); in apic_timer_fn()
2435 if (lapic_is_periodic(apic)) { in apic_timer_fn()
2436 advance_periodic_target_expiration(apic); in apic_timer_fn()
2445 struct kvm_lapic *apic; in kvm_create_lapic() local
2449 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT); in kvm_create_lapic()
2450 if (!apic) in kvm_create_lapic()
2453 vcpu->arch.apic = apic; in kvm_create_lapic()
2455 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); in kvm_create_lapic()
2456 if (!apic->regs) { in kvm_create_lapic()
2457 printk(KERN_ERR "malloc apic regs error for vcpu %x\n", in kvm_create_lapic()
2461 apic->vcpu = vcpu; in kvm_create_lapic()
2463 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, in kvm_create_lapic()
2465 apic->lapic_timer.timer.function = apic_timer_fn; in kvm_create_lapic()
2467 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT; in kvm_create_lapic()
2470 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in kvm_create_lapic()
2475 * APIC is created enabled. This will prevent kvm_lapic_set_base from in kvm_create_lapic()
2476 * thinking that APIC state has changed. in kvm_create_lapic()
2480 kvm_iodevice_init(&apic->dev, &apic_mmio_ops); in kvm_create_lapic()
2484 kfree(apic); in kvm_create_lapic()
2485 vcpu->arch.apic = NULL; in kvm_create_lapic()
2492 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_has_interrupt() local
2498 __apic_update_ppr(apic, &ppr); in kvm_apic_has_interrupt()
2499 return apic_has_interrupt_for_ppr(apic, ppr); in kvm_apic_has_interrupt()
2505 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); in kvm_apic_accept_pic_intr()
2507 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) in kvm_apic_accept_pic_intr()
2517 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_inject_apic_timer_irqs() local
2519 if (atomic_read(&apic->lapic_timer.pending) > 0) { in kvm_inject_apic_timer_irqs()
2520 kvm_apic_inject_pending_timer_irqs(apic); in kvm_inject_apic_timer_irqs()
2521 atomic_set(&apic->lapic_timer.pending, 0); in kvm_inject_apic_timer_irqs()
2528 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_apic_interrupt() local
2535 * We get here even with APIC virtualization enabled, if doing in kvm_get_apic_interrupt()
2541 apic_clear_irr(vector, apic); in kvm_get_apic_interrupt()
2548 apic_update_ppr(apic); in kvm_get_apic_interrupt()
2556 apic_set_isr(vector, apic); in kvm_get_apic_interrupt()
2557 __apic_update_ppr(apic, &ppr); in kvm_get_apic_interrupt()
2566 if (apic_x2apic_mode(vcpu->arch.apic)) { in kvm_apic_state_fixup()
2590 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); in kvm_apic_get_state()
2597 __apic_read(vcpu->arch.apic, APIC_TMCCT)); in kvm_apic_get_state()
2604 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_state() local
2609 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); in kvm_apic_set_state()
2616 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s)); in kvm_apic_set_state()
2618 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_state()
2622 apic_update_ppr(apic); in kvm_apic_set_state()
2623 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_apic_set_state()
2624 apic_update_lvtt(apic); in kvm_apic_set_state()
2625 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); in kvm_apic_set_state()
2626 update_divide_count(apic); in kvm_apic_set_state()
2627 __start_apic_timer(apic, APIC_TMCCT); in kvm_apic_set_state()
2629 apic->highest_isr_cache = -1; in kvm_apic_set_state()
2633 apic_find_highest_irr(apic)); in kvm_apic_set_state()
2635 apic_find_highest_isr(apic)); in kvm_apic_set_state()
2654 timer = &vcpu->arch.apic->lapic_timer.timer; in __kvm_migrate_apic_timer()
2667 struct kvm_lapic *apic) in apic_sync_pv_eoi_from_guest() argument
2692 vector = apic_set_eoi(apic); in apic_sync_pv_eoi_from_guest()
2693 trace_kvm_pv_eoi(apic, vector); in apic_sync_pv_eoi_from_guest()
2701 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); in kvm_lapic_sync_from_vapic()
2706 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_from_vapic()
2710 apic_set_tpr(vcpu->arch.apic, data & 0xff); in kvm_lapic_sync_from_vapic()
2720 struct kvm_lapic *apic) in apic_sync_pv_eoi_to_guest() argument
2724 apic->irr_pending || in apic_sync_pv_eoi_to_guest()
2726 apic->highest_isr_cache == -1 || in apic_sync_pv_eoi_to_guest()
2728 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { in apic_sync_pv_eoi_to_guest()
2736 pv_eoi_set_pending(apic->vcpu); in apic_sync_pv_eoi_to_guest()
2743 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_sync_to_vapic() local
2745 apic_sync_pv_eoi_to_guest(vcpu, apic); in kvm_lapic_sync_to_vapic()
2750 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; in kvm_lapic_sync_to_vapic()
2751 max_irr = apic_find_highest_irr(apic); in kvm_lapic_sync_to_vapic()
2754 max_isr = apic_find_highest_isr(apic); in kvm_lapic_sync_to_vapic()
2759 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_to_vapic()
2767 &vcpu->arch.apic->vapic_cache, in kvm_lapic_set_vapic_addr()
2775 vcpu->arch.apic->vapic_addr = vapic_addr; in kvm_lapic_set_vapic_addr()
2781 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_write() local
2784 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) in kvm_x2apic_msr_write()
2792 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); in kvm_x2apic_msr_write()
2793 return kvm_lapic_reg_write(apic, reg, (u32)data); in kvm_x2apic_msr_write()
2798 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_read() local
2801 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) in kvm_x2apic_msr_read()
2807 if (kvm_lapic_reg_read(apic, reg, 4, &low)) in kvm_x2apic_msr_read()
2810 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); in kvm_x2apic_msr_read()
2819 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_hv_vapic_msr_write() local
2826 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); in kvm_hv_vapic_msr_write()
2827 return kvm_lapic_reg_write(apic, reg, (u32)data); in kvm_hv_vapic_msr_write()
2832 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_hv_vapic_msr_read() local
2838 if (kvm_lapic_reg_read(apic, reg, 4, &low)) in kvm_hv_vapic_msr_read()
2841 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); in kvm_hv_vapic_msr_read()
2871 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_accept_events() local
2875 if (!lapic_in_kernel(vcpu) || !apic->pending_events) in kvm_apic_accept_events()
2888 if (test_bit(KVM_APIC_SIPI, &apic->pending_events)) in kvm_apic_accept_events()
2889 clear_bit(KVM_APIC_SIPI, &apic->pending_events); in kvm_apic_accept_events()
2893 pe = xchg(&apic->pending_events, 0); in kvm_apic_accept_events()
2896 if (kvm_vcpu_is_bsp(apic->vcpu)) in kvm_apic_accept_events()
2905 sipi_vector = apic->sipi_vector; in kvm_apic_accept_events()