35 /* mapping between fixed pmc index and intel_arch_events array */
45 		struct kvm_pmc *pmc;  in reprogram_fixed_counters()  local
47 		pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);  in reprogram_fixed_counters()
53 		reprogram_fixed_counter(pmc, new_ctrl, i);  in reprogram_fixed_counters()
71 static unsigned int intel_pmc_perf_hw_id(struct kvm_pmc *pmc)  in intel_pmc_perf_hw_id()  argument
73 	struct kvm_pmu *pmu = pmc_to_pmu(pmc);  in intel_pmc_perf_hw_id()
74 	u8 event_select = pmc->eventsel & ARCH_PERFMON_EVENTSEL_EVENT;  in intel_pmc_perf_hw_id()
75 	u8 unit_mask = (pmc->eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;  in intel_pmc_perf_hw_id()
102 /* check if a PMC is enabled by comparing it with globl_ctrl bits. */
103 static bool intel_pmc_is_enabled(struct kvm_pmc *pmc)  in intel_pmc_is_enabled()  argument
105 	struct kvm_pmu *pmu = pmc_to_pmu(pmc);  in intel_pmc_is_enabled()
110 	return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);  in intel_pmc_is_enabled()
205 	struct kvm_pmc *pmc;  in intel_msr_idx_to_pmc()  local
207 	pmc = get_fixed_pmc(pmu, msr);  in intel_msr_idx_to_pmc()
208 	pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0);  in intel_msr_idx_to_pmc()
209 	pmc = pmc ? pmc : get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0);  in intel_msr_idx_to_pmc()
211 	return pmc;  in intel_msr_idx_to_pmc()
217 	struct kvm_pmc *pmc;  in intel_pmu_get_msr()  local
234 		if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||  in intel_pmu_get_msr()
235 		    (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {  in intel_pmu_get_msr()
236 			u64 val = pmc_read_counter(pmc);  in intel_pmu_get_msr()
240 		} else if ((pmc = get_fixed_pmc(pmu, msr))) {  in intel_pmu_get_msr()
241 			u64 val = pmc_read_counter(pmc);  in intel_pmu_get_msr()
245 		} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {  in intel_pmu_get_msr()
246 			msr_info->data = pmc->eventsel;  in intel_pmu_get_msr()
257 	struct kvm_pmc *pmc;  in intel_pmu_set_msr()  local
293 		if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||  in intel_pmu_set_msr()
294 		    (pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {  in intel_pmu_set_msr()
301 			pmc->counter += data - pmc_read_counter(pmc);  in intel_pmu_set_msr()
302 			if (pmc->perf_event)  in intel_pmu_set_msr()
303 				perf_event_period(pmc->perf_event,  in intel_pmu_set_msr()
304 						  get_sample_period(pmc, data));  in intel_pmu_set_msr()
306 		} else if ((pmc = get_fixed_pmc(pmu, msr))) {  in intel_pmu_set_msr()
307 			pmc->counter += data - pmc_read_counter(pmc);  in intel_pmu_set_msr()
308 			if (pmc->perf_event)  in intel_pmu_set_msr()
309 				perf_event_period(pmc->perf_event,  in intel_pmu_set_msr()
310 						  get_sample_period(pmc, data));  in intel_pmu_set_msr()
312 		} else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {  in intel_pmu_set_msr()
313 			if (data == pmc->eventsel)  in intel_pmu_set_msr()
316 				reprogram_gp_counter(pmc, data);  in intel_pmu_set_msr()
428 	struct kvm_pmc *pmc = NULL;  in intel_pmu_reset()  local
432 		pmc = &pmu->gp_counters[i];  in intel_pmu_reset()
434 		pmc_stop_counter(pmc);  in intel_pmu_reset()
435 		pmc->counter = pmc->eventsel = 0;  in intel_pmu_reset()
439 		pmc = &pmu->fixed_counters[i];  in intel_pmu_reset()
441 		pmc_stop_counter(pmc);  in intel_pmu_reset()
442 		pmc->counter = 0;  in intel_pmu_reset()