Lines Matching +full:0 +full:xc01
21 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
22 #define PIRQ_VERSION 0x0100
33 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
37 unsigned int pcibios_irq_mask = 0xfff8;
40 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
41 0, 0, 0, 0, 1000, 100000, 100000, 100000
77 sum = 0; in pirq_check_routing_table()
78 for (i = 0; i < rt->size; i++) in pirq_check_routing_table()
81 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", in pirq_check_routing_table()
91 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
105 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { in pirq_find_routing_table()
126 memset(busmap, 0, sizeof(busmap)); in pirq_peer_trick()
127 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { in pirq_peer_trick()
133 for (j = 0; j < 4; j++) in pirq_peer_trick()
141 if (!busmap[i] || pci_find_bus(0, i)) in pirq_peer_trick()
150 * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1.
156 unsigned int port = 0x4d0 + (irq >> 3); in elcr_set_level_irq()
182 return (nr & 1) ? (x >> 4) : (x & 0xf); in read_config_nybble()
192 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); in write_config_nybble()
203 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; in pirq_ali_get()
206 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; in pirq_ali_get()
211 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; in pirq_ali_set()
216 write_config_nybble(router, 0x48, pirq-1, val); in pirq_ali_set()
219 return 0; in pirq_ali_set()
231 return (x < 16) ? x : 0; in pirq_piix_get()
247 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); in pirq_via_get()
252 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); in pirq_via_set()
266 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); in pirq_via586_get()
274 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); in pirq_via586_set()
280 * FIXME: pirqmap may be { 1, 0, 3, 2 },
285 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; in pirq_ite_get()
288 return read_config_nybble(router, 0x43, pirqmap[pirq-1]); in pirq_ite_get()
293 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; in pirq_ite_set()
296 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); in pirq_ite_set()
306 return read_config_nybble(router, 0xb8, pirq >> 4); in pirq_opti_get()
311 write_config_nybble(router, 0xb8, pirq >> 4, irq); in pirq_opti_set()
316 * Cyrix: nibble offset 0x5C
317 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
318 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
322 return read_config_nybble(router, 0x5C, (pirq-1)^1); in pirq_cyrix_get()
327 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); in pirq_cyrix_set()
342 * bit 7 IRQ mapping enabled (0) or disabled (1)
344 * bits [3:0] IRQ to map to
346 * reserved: 0, 1, 2, 8, 13
348 * The config-space registers located at 0x41/0x42/0x43/0x44 are
351 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
357 * router (ISA-bridge) should be 0x01 or 0xb0.
359 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
365 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
367 * 0x61: IDEIRQ:
369 * bit 4 channel-select primary (0), secondary (1)
371 * 0x62: USBIRQ:
372 * bit 6 OHCI function disabled (0), enabled (1)
374 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
376 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
383 * router revision 0x04 and there are changes in the register layout
386 * Onchip routing for router rev-id 0x04 (try-and-error observation)
388 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
392 #define PIRQ_SIS_IRQ_MASK 0x0f
393 #define PIRQ_SIS_IRQ_DISABLE 0x80
394 #define PIRQ_SIS_USB_ENABLE 0x40
402 if (reg >= 0x01 && reg <= 0x04) in pirq_sis_get()
403 reg += 0x40; in pirq_sis_get()
405 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK); in pirq_sis_get()
414 if (reg >= 0x01 && reg <= 0x04) in pirq_sis_set()
415 reg += 0x40; in pirq_sis_set()
425 * VLSI: nibble offset 0x74 - educated guess due to routing table and
437 return 0; in pirq_vlsi_get()
439 return read_config_nybble(router, 0x74, pirq-1); in pirq_vlsi_get()
447 return 0; in pirq_vlsi_set()
449 write_config_nybble(router, 0x74, pirq-1, irq); in pirq_vlsi_set()
455 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
456 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
461 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
462 * and 0x03 for SMBus.
466 outb(pirq, 0xc00); in pirq_serverworks_get()
467 return inb(0xc01) & 0xf; in pirq_serverworks_get()
473 outb(pirq, 0xc00); in pirq_serverworks_set()
474 outb(irq, 0xc01); in pirq_serverworks_set()
480 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
481 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
483 * offset 0x56 0-3 PIRQA 4-7 PIRQB
484 * offset 0x57 0-3 PIRQC 4-7 PIRQD
489 irq = 0; in pirq_amd756_get()
491 irq = read_config_nybble(router, 0x56, pirq - 1); in pirq_amd756_get()
504 write_config_nybble(router, 0x56, pirq - 1, irq); in pirq_amd756_set()
513 outb(0x10 + ((pirq - 1) >> 1), 0x24); in pirq_pico_get()
514 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); in pirq_pico_get()
521 outb(0x10 + ((pirq - 1) >> 1), 0x24); in pirq_pico_set()
522 x = inb(0x26); in pirq_pico_set()
523 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); in pirq_pico_set()
524 outb(x, 0x26); in pirq_pico_set()
549 return 0; in intel_router_probe()
613 return 0; in intel_router_probe()
668 return 0; in via_router_probe()
680 return 0; in vlsi_router_probe()
695 return 0; in serverworks_router_probe()
701 return 0; in sis_router_probe()
718 return 0; in cyrix_router_probe()
730 return 0; in opti_router_probe()
742 return 0; in ite_router_probe()
755 return 0; in ali_router_probe()
771 return 0; in amd_router_probe()
793 return 0; in pico_router_probe()
809 { 0, NULL }
842 pirq_router_dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus, in pirq_find_router()
886 int irq = 0; in pcibios_lookup_irq()
896 return 0; in pcibios_lookup_irq()
900 return 0; in pcibios_lookup_irq()
905 return 0; in pcibios_lookup_irq()
911 return 0; in pcibios_lookup_irq()
917 return 0; in pcibios_lookup_irq()
926 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { in pcibios_lookup_irq()
935 pirq = 0x68; in pcibios_lookup_irq()
936 mask = 0x400; in pcibios_lookup_irq()
948 newirq = 0; in pcibios_lookup_irq()
954 for (i = 0; i < 16; i++) { in pcibios_lookup_irq()
965 if ((pirq & 0xf0) == 0xf0) { in pcibios_lookup_irq()
966 irq = pirq & 0xf; in pcibios_lookup_irq()
987 return 0; in pcibios_lookup_irq()
1040 dev->irq = 0; in pcibios_fixup_irqs()
1048 pirq_penalty[dev->irq] = 0; in pcibios_fixup_irqs()
1065 pcibios_lookup_irq(dev, 0); in pcibios_fixup_irqs()
1080 return 0; in fix_broken_hp_bios_irq9()
1094 return 0; in fix_acer_tm360_irqrouting()
1144 for (i = 0; i < 16; i++) in pcibios_irq_init()
1199 u8 pin = 0; in pirq_enable_irq()
1206 return 0; in pirq_enable_irq()
1213 if (dev->irq_managed && dev->irq > 0) in pirq_enable_irq()
1214 return 0; in pirq_enable_irq()
1225 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ in pirq_enable_irq()
1232 if (irq >= 0) in pirq_enable_irq()
1240 if (irq >= 0) { in pirq_enable_irq()
1245 return 0; in pirq_enable_irq()
1259 !(dev->class & 0x5)) in pirq_enable_irq()
1260 return 0; in pirq_enable_irq()
1265 return 0; in pirq_enable_irq()
1285 dev->irq = 0; in pirq_disable_irq()
1286 dev->irq_managed = 0; in pirq_disable_irq()