Lines Matching +full:fis +full:- +full:based
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
7 * Based on preview driver from Silicon Image.
17 #include <linux/dma-mapping.h>
33 u8 fis[6 * 4]; member
57 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
113 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
114 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
117 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
135 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
136 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
149 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
161 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
177 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
182 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
183 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
184 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
185 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
191 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
192 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
193 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
194 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
195 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
196 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
197 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
198 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
199 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
200 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
201 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
202 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
203 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
240 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
268 "device error via D2H FIS" },
270 "device error via SDB FIS" },
272 "error in data FIS" },
274 "failed to transmit command FIS" },
310 "FIS received while sending service FIS" },
314 * ap->private_data
418 * Use bits 30-31 of port_flags to encode available port numbers.
421 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
461 return ap->port_no * PORT_REGS_SIZE; in sil24_port_offset()
466 return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap); in sil24_port_base()
471 void __iomem *port = sil24_port_base(dev->link->ap); in sil24_dev_config()
473 if (dev->cdb_len == 16) in sil24_dev_config()
483 u8 fis[6 * 4]; in sil24_read_tf() local
486 memcpy_fromio(fis, prb->fis, sizeof(fis)); in sil24_read_tf()
487 ata_tf_from_fis(fis, tf); in sil24_read_tf()
499 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; in sil24_scr_read()
505 return -EINVAL; in sil24_scr_read()
510 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; in sil24_scr_write()
516 return -EINVAL; in sil24_scr_write()
524 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) in sil24_config_port()
572 struct sil24_port_priv *pp = ap->private_data; in sil24_init_port()
586 pp->do_port_rst = 1; in sil24_init_port()
587 ap->link.eh_context.i.action |= ATA_EH_RESET; in sil24_init_port()
588 return -EIO; in sil24_init_port()
600 struct sil24_port_priv *pp = ap->private_data; in sil24_exec_polled_cmd()
601 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; in sil24_exec_polled_cmd()
602 dma_addr_t paddr = pp->cmd_block_dma; in sil24_exec_polled_cmd()
606 prb->ctrl = cpu_to_le16(ctrl); in sil24_exec_polled_cmd()
607 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis); in sil24_exec_polled_cmd()
635 rc = -EIO; in sil24_exec_polled_cmd()
637 rc = -EBUSY; in sil24_exec_polled_cmd()
649 struct ata_port *ap = link->ap; in sil24_softreset()
666 timeout_msec = jiffies_to_msecs(deadline - jiffies); in sil24_softreset()
668 ata_tf_init(link->device, &tf); /* doesn't really matter */ in sil24_softreset()
671 if (rc == -EBUSY) { in sil24_softreset()
687 return -EIO; in sil24_softreset()
693 struct ata_port *ap = link->ap; in sil24_hardreset()
695 struct sil24_port_priv *pp = ap->private_data; in sil24_hardreset()
705 if (pp->do_port_rst) { in sil24_hardreset()
717 sil24_config_pmp(ap, ap->nr_pmp_links); in sil24_hardreset()
719 pp->do_port_rst = 0; in sil24_hardreset()
751 /* Sil24 doesn't store signature FIS after hardreset, so we in sil24_hardreset()
754 * for BSY clearance here. Tell libata to perform follow-up in sil24_hardreset()
757 return -EAGAIN; in sil24_hardreset()
761 pp->do_port_rst = 1; in sil24_hardreset()
766 return -EIO; in sil24_hardreset()
776 for_each_sg(qc->sg, sg, qc->n_elem, si) { in sil24_fill_sg()
777 sge->addr = cpu_to_le64(sg_dma_address(sg)); in sil24_fill_sg()
778 sge->cnt = cpu_to_le32(sg_dma_len(sg)); in sil24_fill_sg()
779 sge->flags = 0; in sil24_fill_sg()
785 last_sge->flags = cpu_to_le32(SGE_TRM); in sil24_fill_sg()
790 struct ata_link *link = qc->dev->link; in sil24_qc_defer()
791 struct ata_port *ap = link->ap; in sil24_qc_defer()
792 u8 prot = qc->tf.protocol; in sil24_qc_defer()
808 * - ATAPI commands which check the sense data in sil24_qc_defer()
809 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF in sil24_qc_defer()
814 (qc->flags & ATA_QCFLAG_RESULT_TF)); in sil24_qc_defer()
816 if (unlikely(ap->excl_link)) { in sil24_qc_defer()
817 if (link == ap->excl_link) { in sil24_qc_defer()
818 if (ap->nr_active_links) in sil24_qc_defer()
820 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; in sil24_qc_defer()
824 ap->excl_link = link; in sil24_qc_defer()
825 if (ap->nr_active_links) in sil24_qc_defer()
827 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; in sil24_qc_defer()
835 struct ata_port *ap = qc->ap; in sil24_qc_prep()
836 struct sil24_port_priv *pp = ap->private_data; in sil24_qc_prep()
842 cb = &pp->cmd_block[sil24_tag(qc->hw_tag)]; in sil24_qc_prep()
844 if (!ata_is_atapi(qc->tf.protocol)) { in sil24_qc_prep()
845 prb = &cb->ata.prb; in sil24_qc_prep()
846 sge = cb->ata.sge; in sil24_qc_prep()
847 if (ata_is_data(qc->tf.protocol)) { in sil24_qc_prep()
850 if (ata_is_ncq(qc->tf.protocol)) in sil24_qc_prep()
852 if (qc->tf.flags & ATA_TFLAG_WRITE) in sil24_qc_prep()
856 prb->prot = cpu_to_le16(prot); in sil24_qc_prep()
859 prb = &cb->atapi.prb; in sil24_qc_prep()
860 sge = cb->atapi.sge; in sil24_qc_prep()
861 memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb)); in sil24_qc_prep()
862 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); in sil24_qc_prep()
864 if (ata_is_data(qc->tf.protocol)) { in sil24_qc_prep()
865 if (qc->tf.flags & ATA_TFLAG_WRITE) in sil24_qc_prep()
872 prb->ctrl = cpu_to_le16(ctrl); in sil24_qc_prep()
873 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis); in sil24_qc_prep()
875 if (qc->flags & ATA_QCFLAG_DMAMAP) in sil24_qc_prep()
883 struct ata_port *ap = qc->ap; in sil24_qc_issue()
884 struct sil24_port_priv *pp = ap->private_data; in sil24_qc_issue()
886 unsigned int tag = sil24_tag(qc->hw_tag); in sil24_qc_issue()
890 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); in sil24_qc_issue()
906 sil24_read_tf(qc->ap, qc->hw_tag, &qc->result_tf); in sil24_qc_fill_rtf()
912 u32 *gscr = ap->link.device->gscr; in sil24_pmp_attach()
920 "disabling NCQ support due to sil24-mv4140 quirk\n"); in sil24_pmp_attach()
921 ap->flags &= ~ATA_FLAG_NCQ; in sil24_pmp_attach()
930 ap->flags |= ATA_FLAG_NCQ; in sil24_pmp_detach()
938 rc = sil24_init_port(link->ap); in sil24_pmp_hardreset()
951 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear in sil24_freeze()
973 struct sil24_port_priv *pp = ap->private_data; in sil24_error_intr()
985 link = &ap->link; in sil24_error_intr()
986 ehi = &link->eh_info; in sil24_error_intr()
1005 ehi->err_mask |= AC_ERR_HSM; in sil24_error_intr()
1006 ehi->action |= ATA_EH_RESET; in sil24_error_intr()
1007 ata_ehi_push_desc(ehi, "unknown FIS"); in sil24_error_intr()
1025 if (ap->nr_active_links >= 3) { in sil24_error_intr()
1026 ehi->err_mask |= AC_ERR_OTHER; in sil24_error_intr()
1027 ehi->action |= ATA_EH_RESET; in sil24_error_intr()
1029 pp->do_port_rst = 1; in sil24_error_intr()
1038 if (pmp < ap->nr_pmp_links) { in sil24_error_intr()
1039 link = &ap->pmp_link[pmp]; in sil24_error_intr()
1040 ehi = &link->eh_info; in sil24_error_intr()
1041 qc = ata_qc_from_tag(ap, link->active_tag); in sil24_error_intr()
1052 qc = ata_qc_from_tag(ap, link->active_tag); in sil24_error_intr()
1059 if (ci && ci->desc) { in sil24_error_intr()
1060 err_mask |= ci->err_mask; in sil24_error_intr()
1061 action |= ci->action; in sil24_error_intr()
1064 ata_ehi_push_desc(ehi, "%s", ci->desc); in sil24_error_intr()
1075 qc->err_mask |= err_mask; in sil24_error_intr()
1077 ehi->err_mask |= err_mask; in sil24_error_intr()
1079 ehi->action |= action; in sil24_error_intr()
1091 ata_link_abort(qc->dev->link); in sil24_error_intr()
1110 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) in sil24_host_intr()
1125 struct ata_eh_info *ehi = &ap->link.eh_info; in sil24_host_intr()
1126 ehi->err_mask |= AC_ERR_HSM; in sil24_host_intr()
1127 ehi->action |= ATA_EH_RESET; in sil24_host_intr()
1133 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit()) in sil24_host_intr()
1136 slot_stat, ap->link.active_tag, ap->link.sactive); in sil24_host_intr()
1142 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; in sil24_interrupt()
1150 dev_err(host->dev, "IRQ status == 0xffffffff, " in sil24_interrupt()
1158 spin_lock(&host->lock); in sil24_interrupt()
1160 for (i = 0; i < host->n_ports; i++) in sil24_interrupt()
1162 sil24_host_intr(host->ports[i]); in sil24_interrupt()
1166 spin_unlock(&host->lock); in sil24_interrupt()
1173 struct sil24_port_priv *pp = ap->private_data; in sil24_error_handler()
1180 pp->do_port_rst = 0; in sil24_error_handler()
1185 struct ata_port *ap = qc->ap; in sil24_post_internal_cmd()
1188 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap)) in sil24_post_internal_cmd()
1194 struct device *dev = ap->host->dev; in sil24_port_start()
1202 return -ENOMEM; in sil24_port_start()
1206 return -ENOMEM; in sil24_port_start()
1208 pp->cmd_block = cb; in sil24_port_start()
1209 pp->cmd_block_dma = cb_dma; in sil24_port_start()
1211 ap->private_data = pp; in sil24_port_start()
1213 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host"); in sil24_port_start()
1221 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; in sil24_init_controller()
1232 for (i = 0; i < host->n_ports; i++) { in sil24_init_controller()
1233 struct ata_port *ap = host->ports[i]; in sil24_init_controller()
1248 dev_err(host->dev, in sil24_init_controller()
1263 struct ata_port_info pi = sil24_port_info[ent->driver_data]; in sil24_init_one()
1274 ata_print_version_once(&pdev->dev, DRV_VERSION); in sil24_init_one()
1288 /* apply workaround for completion IRQ loss on PCI-X errata */ in sil24_init_one()
1292 dev_info(&pdev->dev, in sil24_init_one()
1293 "Applying completion IRQ loss on PCI-X errata fix\n"); in sil24_init_one()
1299 host = ata_host_alloc_pinfo(&pdev->dev, ppi, in sil24_init_one()
1300 SIL24_FLAG2NPORTS(ppi[0]->flags)); in sil24_init_one()
1302 return -ENOMEM; in sil24_init_one()
1303 host->iomap = iomap; in sil24_init_one()
1306 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in sil24_init_one()
1308 dev_err(&pdev->dev, "DMA enable failed\n"); in sil24_init_one()
1313 * write throughput for pci-e variants. in sil24_init_one()
1320 dev_info(&pdev->dev, "Using MSI\n"); in sil24_init_one()
1325 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED, in sil24_init_one()
1333 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; in sil24_pci_device_resume()
1340 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) in sil24_pci_device_resume()
1354 sil24_config_pmp(ap, ap->nr_pmp_links); in sil24_port_resume()
1362 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");