Lines Matching +full:c +full:- +full:22
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* drivers/atm/firestream.h - FireStream 155 (MB86697) and
6 /* Written & (C) 2000 by R.E.Wolff@BitWizard.nl
7 * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA
8 * and ambassador.c Copyright (C) 1995-1999 Madge Networks Ltd
50 #define STATUS_CODE(qe) ((qe->cmd >> 22) & 0x3f)
98 #define QE_CMD_NULL (0x00 << 22)
99 #define QE_CMD_REG_RD (0x01 << 22)
100 #define QE_CMD_REG_RDM (0x02 << 22)
101 #define QE_CMD_REG_WR (0x03 << 22)
102 #define QE_CMD_REG_WRM (0x04 << 22)
103 #define QE_CMD_CONFIG_TX (0x05 << 22)
104 #define QE_CMD_CONFIG_RX (0x06 << 22)
105 #define QE_CMD_PRP_RD (0x07 << 22)
106 #define QE_CMD_PRP_RDM (0x2a << 22)
107 #define QE_CMD_PRP_WR (0x09 << 22)
108 #define QE_CMD_PRP_WRM (0x2b << 22)
109 #define QE_CMD_RX_EN (0x0a << 22)
110 #define QE_CMD_RX_PURGE (0x0b << 22)
111 #define QE_CMD_RX_PURGE_INH (0x0c << 22)
112 #define QE_CMD_TX_EN (0x0d << 22)
113 #define QE_CMD_TX_PURGE (0x0e << 22)
114 #define QE_CMD_TX_PURGE_INH (0x0f << 22)
115 #define QE_CMD_RST_CG (0x10 << 22)
116 #define QE_CMD_SET_CG (0x11 << 22)
117 #define QE_CMD_RST_CLP (0x12 << 22)
118 #define QE_CMD_SET_CLP (0x13 << 22)
119 #define QE_CMD_OVERRIDE (0x14 << 22)
120 #define QE_CMD_ADD_BFP (0x15 << 22)
121 #define QE_CMD_DUMP_TX (0x16 << 22)
122 #define QE_CMD_DUMP_RX (0x17 << 22)
123 #define QE_CMD_LRAM_RD (0x18 << 22)
124 #define QE_CMD_LRAM_RDM (0x28 << 22)
125 #define QE_CMD_LRAM_WR (0x19 << 22)
126 #define QE_CMD_LRAM_WRM (0x29 << 22)
127 #define QE_CMD_LRAM_BSET (0x1a << 22)
128 #define QE_CMD_LRAM_BCLR (0x1b << 22)
129 #define QE_CMD_CONFIG_SEGM (0x1c << 22)
130 #define QE_CMD_READ_SEGM (0x1d << 22)
131 #define QE_CMD_CONFIG_ROUT (0x1e << 22)
132 #define QE_CMD_READ_ROUT (0x1f << 22)
133 #define QE_CMD_CONFIG_TM (0x20 << 22)
134 #define QE_CMD_READ_TM (0x21 << 22)
135 #define QE_CMD_CONFIG_TXBM (0x22 << 22)
136 #define QE_CMD_READ_TXBM (0x23 << 22)
137 #define QE_CMD_CONFIG_RXBM (0x24 << 22)
138 #define QE_CMD_READ_RXBM (0x25 << 22)
139 #define QE_CMD_CONFIG_REAS (0x26 << 22)
140 #define QE_CMD_READ_REAS (0x27 << 22)
172 * they are now. -- REW
207 be 9. Tell me you don't believe me. -- REW */
270 #define SARMODE1_GNAM (0x1 << 22)
306 #define ISR_PCI_FTL (0x1 << 22)
371 #define TC_FLAGS_TYPE_ABR (0x0 << 22)
372 #define TC_FLAGS_TYPE_CBR (0x1 << 22)
373 #define TC_FLAGS_TYPE_VBR (0x2 << 22)
374 #define TC_FLAGS_TYPE_UBR (0x3 << 22)
409 #define RC_FLAGS_TEVC (0x1 << 22)
486 #define FS_DEV(atm_dev) ((struct fs_dev *) (atm_dev)->dev_data)
487 #define FS_VCC(atm_vcc) ((struct fs_vcc *) (atm_vcc)->dev_data)
493 #define IS_FS50(dev) (dev->flags & FS_IS50)
494 #define IS_FS155(dev) (dev->flags & FS_IS155)
496 /* Within limits this is user-configurable. */
497 /* Note: Currently the sum (10 -> 1k channels) is hardcoded in the driver. */