Lines Matching +full:input +full:- +full:clock +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
30 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
33 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
36 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
39 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
42 /* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */
45 /* MAX_VCO_FREQ: maximum VCO frequency, in Hz (Fvco_max) */
68 * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
69 * @post_divr_freq: input clock rate after the R divider
71 * Select the value to be presented to the PLL RANGE input signals, based
72 * on the input clock frequency after the post-R-divider @post_divr_freq.
83 WARN(1, "%s: post-divider reference freq out of range: %lu", in __wrpll_calc_filter_range()
85 return -ERANGE; in __wrpll_calc_filter_range()
107 * __wrpll_calc_fbdiv() - return feedback fixed divide value
110 * The internal feedback path includes a fixed by-two divider; the
125 return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1; in __wrpll_calc_fbdiv()
129 * __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate
130 * @target_rate: target PLL output clock rate
133 * Determine a reasonable value for the PLL Q post-divider, based on the
171 * __wrpll_update_parent_rate() - update PLL data when parent rate changes
173 * @parent_rate: PLL input refclk rate (pre-R-divider)
175 * Pre-compute some data used by the PLL configuration algorithm when
176 * the PLL's reference clock rate changes. The intention is to avoid
177 * computation when the parent rate remains constant - expected to be
180 * Returns: 0 upon success or -ERANGE if the reference clock rate is
189 return -ERANGE; in __wrpll_update_parent_rate()
191 c->parent_rate = parent_rate; in __wrpll_update_parent_rate()
193 c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent); in __wrpll_update_parent_rate()
195 c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ); in __wrpll_update_parent_rate()
201 * wrpll_configure() - compute PLL configuration for a target rate
203 * @target_rate: target PLL output clock rate (post-Q-divider)
204 * @parent_rate: PLL input refclk rate (pre-R-divider)
208 * caller should switch any downstream logic to a different clock
209 * source or clock-gate it before presenting these values to the PLL
212 * The caller must pass this function a pre-initialized struct
230 if (c->flags == 0) { in wrpll_configure_for_rate()
232 return -EINVAL; in wrpll_configure_for_rate()
236 if (parent_rate != c->parent_rate) { in wrpll_configure_for_rate()
238 pr_err("%s: PLL input rate is out of range\n", in wrpll_configure_for_rate()
240 return -ERANGE; in wrpll_configure_for_rate()
244 c->flags &= ~WRPLL_FLAGS_RESET_MASK; in wrpll_configure_for_rate()
246 /* Put the PLL into bypass if the user requests the parent clock rate */ in wrpll_configure_for_rate()
248 c->flags |= WRPLL_FLAGS_BYPASS_MASK; in wrpll_configure_for_rate()
252 c->flags &= ~WRPLL_FLAGS_BYPASS_MASK; in wrpll_configure_for_rate()
257 return -1; in wrpll_configure_for_rate()
258 c->divq = divq; in wrpll_configure_for_rate()
260 /* Precalculate the pre-Q divider target ratio */ in wrpll_configure_for_rate()
272 for (r = c->init_r; r <= c->max_r; ++r) { in wrpll_configure_for_rate()
275 f >>= (fbdiv - 1); in wrpll_configure_for_rate()
283 --f; in wrpll_configure_for_rate()
290 delta = abs(target_rate - vco); in wrpll_configure_for_rate()
298 c->divr = best_r - 1; in wrpll_configure_for_rate()
299 c->divf = best_f - 1; in wrpll_configure_for_rate()
307 c->range = range; in wrpll_configure_for_rate()
313 * wrpll_calc_output_rate() - calculate the PLL's target output rate
317 * Given a pointer to the PLL's current input configuration @c and the
318 * PLL's input reference clock rate @parent_rate (before the R
319 * pre-divider), calculate the PLL's output clock rate (after the Q
320 * post-divider).
325 * Return: the PLL's output clock rate, in Hz. The return value from
327 * to the Linux clock framework; thus there is no explicit
336 if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) { in wrpll_calc_output_rate()
342 n = parent_rate * fbdiv * (c->divf + 1); in wrpll_calc_output_rate()
343 n = div_u64(n, c->divr + 1); in wrpll_calc_output_rate()
344 n >>= c->divq; in wrpll_calc_output_rate()
350 * wrpll_calc_max_lock_us() - return the time for the PLL to lock
355 * to the input frequency and stable. This is likely to depend on the DIVR