13 #include <linux/clk-provider.h>
32  * |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
37  * reg should be an u32 variable.
40 #define PLL_REG_GET_LOW(reg)			\  argument
41 	(((reg) & (0x3F << 0)) >> 0)
42 #define PLL_REG_GET_HIGH(reg)			\  argument
43 	(((reg) & (0x3F << 6)) >> 6)
44 #define PLL_REG_GET_EDGE(reg)			\  argument
45 	(((reg) & (BIT(12))) ? 1 : 0)
46 #define PLL_REG_GET_BYPASS(reg)			\  argument
47 	(((reg) & (BIT(13))) ? 1 : 0)
48 #define PLL_REG_GET_NOUPD(reg)			\  argument
49 	(((reg) & (BIT(14))) ? 1 : 0)
50 #define PLL_REG_GET_PAD(reg)			\  argument
51 	(((reg) & (0x1FFFF << 15)) >> 15)
53 #define PLL_REG_SET_LOW(reg, value)		\  argument
54 	{ reg |= (((value) & 0x3F) << 0); }
55 #define PLL_REG_SET_HIGH(reg, value)		\  argument
56 	{ reg |= (((value) & 0x3F) << 6); }
57 #define PLL_REG_SET_EDGE(reg, value)		\  argument
58 	{ reg |= (((value) & 0x01) << 12); }
59 #define PLL_REG_SET_BYPASS(reg, value)		\  argument
60 	{ reg |= (((value) & 0x01) << 13); }
61 #define PLL_REG_SET_NOUPD(reg, value)		\  argument
62 	{ reg |= (((value) & 0x01) << 14); }
63 #define PLL_REG_SET_PAD(reg, value)		\  argument
64 	{ reg |= (((value) & 0x1FFFF) << 15); }
102 static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,  in axs10x_pll_write()  argument
105 	iowrite32(val, clk->base + reg);  in axs10x_pll_write()
108 static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)  in axs10x_pll_read()  argument
110 	return ioread32(clk->base + reg);  in axs10x_pll_read()
118 static inline u32 axs10x_div_get_value(u32 reg)  in axs10x_div_get_value()  argument
120 	if (PLL_REG_GET_BYPASS(reg))  in axs10x_div_get_value()
123 	return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);  in axs10x_div_get_value()
162 	const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;  in axs10x_pll_round_rate()
165 		return -EINVAL;  in axs10x_pll_round_rate()
170 		if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))  in axs10x_pll_round_rate()
182 	const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;  in axs10x_pll_set_rate()
198 			if (!(ioread32(clk->lock) & PLL_LOCK))  in axs10x_pll_set_rate()
199 				return -ETIMEDOUT;  in axs10x_pll_set_rate()
201 			if (ioread32(clk->lock) & PLL_ERROR)  in axs10x_pll_set_rate()
202 				return -EINVAL;  in axs10x_pll_set_rate()
208 	dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,  in axs10x_pll_set_rate()
210 	return -EINVAL;  in axs10x_pll_set_rate()
221 	struct device *dev = &pdev->dev;  in axs10x_pll_clk_probe()
224 	struct clk_init_data init = { };  in axs10x_pll_clk_probe()  local
229 		return -ENOMEM;  in axs10x_pll_clk_probe()
231 	pll_clk->base = devm_platform_ioremap_resource(pdev, 0);  in axs10x_pll_clk_probe()
232 	if (IS_ERR(pll_clk->base))  in axs10x_pll_clk_probe()
233 		return PTR_ERR(pll_clk->base);  in axs10x_pll_clk_probe()
235 	pll_clk->lock = devm_platform_ioremap_resource(pdev, 1);  in axs10x_pll_clk_probe()
236 	if (IS_ERR(pll_clk->lock))  in axs10x_pll_clk_probe()
237 		return PTR_ERR(pll_clk->lock);  in axs10x_pll_clk_probe()
239 	init.name = dev->of_node->name;  in axs10x_pll_clk_probe()
240 	init.ops = &axs10x_pll_ops;  in axs10x_pll_clk_probe()
241 	parent_name = of_clk_get_parent_name(dev->of_node, 0);  in axs10x_pll_clk_probe()
242 	init.parent_names = &parent_name;  in axs10x_pll_clk_probe()
243 	init.num_parents = 1;  in axs10x_pll_clk_probe()
244 	pll_clk->hw.init = &init;  in axs10x_pll_clk_probe()
245 	pll_clk->dev = dev;  in axs10x_pll_clk_probe()
246 	pll_clk->pll_cfg = of_device_get_match_data(dev);  in axs10x_pll_clk_probe()
248 	if (!pll_clk->pll_cfg) {  in axs10x_pll_clk_probe()
250 		return -EINVAL;  in axs10x_pll_clk_probe()
253 	ret = devm_clk_hw_register(dev, &pll_clk->hw);  in axs10x_pll_clk_probe()
255 		dev_err(dev, "failed to register %s clock\n", init.name);  in axs10x_pll_clk_probe()
259 	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,  in axs10x_pll_clk_probe()
260 			&pll_clk->hw);  in axs10x_pll_clk_probe()
265 	of_clk_del_provider(pdev->dev.of_node);  in axs10x_pll_clk_remove()
273 	struct clk_init_data init = { };  in of_axs10x_pll_clk_setup()  local
280 	pll_clk->base = of_iomap(node, 0);  in of_axs10x_pll_clk_setup()
281 	if (!pll_clk->base) {  in of_axs10x_pll_clk_setup()
286 	pll_clk->lock = of_iomap(node, 1);  in of_axs10x_pll_clk_setup()
287 	if (!pll_clk->lock) {  in of_axs10x_pll_clk_setup()
292 	init.name = node->name;  in of_axs10x_pll_clk_setup()
293 	init.ops = &axs10x_pll_ops;  in of_axs10x_pll_clk_setup()
295 	init.parent_names = &parent_name;  in of_axs10x_pll_clk_setup()
296 	init.num_parents = parent_name ? 1 : 0;  in of_axs10x_pll_clk_setup()
297 	pll_clk->hw.init = &init;  in of_axs10x_pll_clk_setup()
298 	pll_clk->pll_cfg = arc_pll_cfg;  in of_axs10x_pll_clk_setup()
300 	ret = clk_hw_register(NULL, &pll_clk->hw);  in of_axs10x_pll_clk_setup()
306 	ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);  in of_axs10x_pll_clk_setup()
315 	clk_hw_unregister(&pll_clk->hw);  in of_axs10x_pll_clk_setup()
317 	iounmap(pll_clk->lock);  in of_axs10x_pll_clk_setup()
319 	iounmap(pll_clk->base);  in of_axs10x_pll_clk_setup()
323 CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock",
327 	{ .compatible = "snps,axs10x-pgu-pll-clock", .data = &pgu_pll_cfg},
334 		.name = "axs10x-pll-clock",