Lines Matching +full:es +full:- +full:enable

16 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/bcm-cygnus.h>
24 #include "clk-iproc.h"
33 #define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \  argument
34 		{ .offset = o, .en_shift = es, .high_shift = hs, \
46 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \  argument
49 #define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }  argument
55 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
75 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
81 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
87 		.enable = ENABLE_VAL(0x4, 8, 2, 14),
93 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
99 		.enable = ENABLE_VAL(0x4, 10, 4, 16),
105 		.enable = ENABLE_VAL(0x4, 11, 5, 17),
115 CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);
133 		.enable = ENABLE_VAL(0x0, 7, 1, 13),
139 		.enable = ENABLE_VAL(0x0, 8, 2, 14),
145 		.enable = ENABLE_VAL(0x0, 9, 3, 15),
151 		.enable = ENABLE_VAL(0x0, 10, 4, 16),
157 		.enable = ENABLE_VAL(0x0, 11, 5, 17),
163 		.enable = ENABLE_VAL(0x0, 12, 6, 18),
173 CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init);
211 		.enable = ENABLE_VAL(0x4, 12, 6, 18),
217 		.enable = ENABLE_VAL(0x4, 13, 7, 19),
223 		.enable = ENABLE_VAL(0x4, 14, 8, 20),
229 		.enable = ENABLE_VAL(0x4, 15, 9, 21),
235 		.enable = ENABLE_VAL(0x4, 16, 10, 22),
241 		.enable = ENABLE_VAL(0x4, 17, 11, 23),
252 CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
270 CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
291 		.enable = ENABLE_VAL(0x14, 8, 10, 9),
297 		.enable = ENABLE_VAL(0x18, 8, 10, 9),
303 		.enable = ENABLE_VAL(0x1c, 8, 10, 9),
313 CLK_OF_DECLARE(cygnus_audiopll, "brcm,cygnus-audiopll",