1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright 2012-2013 Analog Devices Inc.
6  *  Author: Lars-Peter Clausen <lars@metafoo.de>
10 #include <linux/clk-provider.h>
61 	case 2:  in axi_clkgen_lookup_filter()
79 	default:  in axi_clkgen_lookup_filter()
113 	unsigned long f, dout, best_f, fvco;  in axi_clkgen_calc_params()  local
142 			dout = DIV_ROUND_CLOSEST(fvco, fout);  in axi_clkgen_calc_params()
143 			dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift);  in axi_clkgen_calc_params()
144 			f = fvco / dout;  in axi_clkgen_calc_params()
145 			if (abs(f - fout) < abs(best_f - fout)) {  in axi_clkgen_calc_params()
148 				*best_m = m << (3 - fract_shift);  in axi_clkgen_calc_params()
149 				*best_dout = dout << (3 - fract_shift);  in axi_clkgen_calc_params()
182 		params->nocount = 1;  in axi_clkgen_calc_clk_params()
187 		params->high = divider / 2;  in axi_clkgen_calc_clk_params()
188 		params->edge = divider % 2;  in axi_clkgen_calc_clk_params()
189 		params->low = divider - params->high;  in axi_clkgen_calc_clk_params()
191 		params->frac_en = 1;  in axi_clkgen_calc_clk_params()
192 		params->frac = frac_divider;  in axi_clkgen_calc_clk_params()
194 		params->high = divider / 2;  in axi_clkgen_calc_clk_params()
195 		params->edge = divider % 2;  in axi_clkgen_calc_clk_params()
196 		params->low = params->high;  in axi_clkgen_calc_clk_params()
198 		if (params->edge == 0) {  in axi_clkgen_calc_clk_params()
199 			params->high--;  in axi_clkgen_calc_clk_params()
200 			params->frac_wf_r = 1;  in axi_clkgen_calc_clk_params()
203 		if (params->edge == 0 || frac_divider == 1)  in axi_clkgen_calc_clk_params()
204 			params->low--;  in axi_clkgen_calc_clk_params()
205 		if (((params->edge == 0) ^ (frac_divider == 1)) ||  in axi_clkgen_calc_clk_params()
206 			(divider == 2 && frac_divider == 1))  in axi_clkgen_calc_clk_params()
207 			params->frac_wf_f = 1;  in axi_clkgen_calc_clk_params()
209 		params->frac_phase = params->edge * 4 + frac_divider / 2;  in axi_clkgen_calc_clk_params()
216 	writel(val, axi_clkgen->base + reg);  in axi_clkgen_write()
222 	*val = readl(axi_clkgen->base + reg);  in axi_clkgen_read()
232 	} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);  in axi_clkgen_wait_non_busy()
235 		return -EIO;  in axi_clkgen_wait_non_busy()
307 		(params->high << 6) | params->low, 0xefff);  in axi_clkgen_set_div()
309 		(params->frac << 12) | (params->frac_en << 11) |  in axi_clkgen_set_div()
310 		(params->frac_wf_r << 10) | (params->edge << 7) |  in axi_clkgen_set_div()
311 		(params->nocount << 6), 0x7fff);  in axi_clkgen_set_div()
314 			(params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);  in axi_clkgen_set_div()
322 	unsigned int d, m, dout;  in axi_clkgen_set_rate()  local
329 		return -EINVAL;  in axi_clkgen_set_rate()
331 	axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);  in axi_clkgen_set_rate()
333 	if (d == 0 || dout == 0 || m == 0)  in axi_clkgen_set_rate()
334 		return -EINVAL;  in axi_clkgen_set_rate()
336 	if ((dout & 0x7) != 0 || (m & 0x7) != 0)  in axi_clkgen_set_rate()
341 	filter = axi_clkgen_lookup_filter(m - 1);  in axi_clkgen_set_rate()
342 	lock = axi_clkgen_lookup_lock(m - 1);  in axi_clkgen_set_rate()
344 	axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, &params);  in axi_clkgen_set_rate()
371 	unsigned int d, m, dout;  in axi_clkgen_round_rate()  local
374 	axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);  in axi_clkgen_round_rate()
376 	if (d == 0 || dout == 0 || m == 0)  in axi_clkgen_round_rate()
377 		return -EINVAL;  in axi_clkgen_round_rate()
380 	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);  in axi_clkgen_round_rate()
416 	unsigned int d, m, dout;  in axi_clkgen_recalc_rate()  local
420 	dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,  in axi_clkgen_recalc_rate()
431 	if (d == 0 || dout == 0)  in axi_clkgen_recalc_rate()
435 	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);  in axi_clkgen_recalc_rate()
487 		.compatible = "adi,axi-clkgen-2.00.a",
498 	const char *parent_names[2];  in axi_clkgen_probe()
504 	if (!pdev->dev.of_node)  in axi_clkgen_probe()
505 		return -ENODEV;  in axi_clkgen_probe()
507 	id = of_match_node(axi_clkgen_ids, pdev->dev.of_node);  in axi_clkgen_probe()
509 		return -ENODEV;  in axi_clkgen_probe()
511 	axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);  in axi_clkgen_probe()
513 		return -ENOMEM;  in axi_clkgen_probe()
516 	axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);  in axi_clkgen_probe()
517 	if (IS_ERR(axi_clkgen->base))  in axi_clkgen_probe()
518 		return PTR_ERR(axi_clkgen->base);  in axi_clkgen_probe()
520 	init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);  in axi_clkgen_probe()
521 	if (init.num_parents < 1 || init.num_parents > 2)  in axi_clkgen_probe()
522 		return -EINVAL;  in axi_clkgen_probe()
525 		parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);  in axi_clkgen_probe()
527 			return -EINVAL;  in axi_clkgen_probe()
530 	clk_name = pdev->dev.of_node->name;  in axi_clkgen_probe()
531 	of_property_read_string(pdev->dev.of_node, "clock-output-names",  in axi_clkgen_probe()
541 	axi_clkgen->clk_hw.init = &init;  in axi_clkgen_probe()
542 	ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);  in axi_clkgen_probe()
546 	return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,  in axi_clkgen_probe()
547 				      &axi_clkgen->clk_hw);  in axi_clkgen_probe()
552 	of_clk_del_provider(pdev->dev.of_node);  in axi_clkgen_remove()
559 		.name = "adi-axi-clkgen",
568 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");