Lines Matching +full:spread +full:- +full:spectrum +full:- +full:center
5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
14 #include <linux/clk-provider.h>
68 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
106 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate()
161 data->m = 0; /* Bypass mode */ in cdce925_pll_set_rate()
162 data->n = 0; in cdce925_pll_set_rate()
169 return -EINVAL; in cdce925_pll_set_rate()
175 return -EINVAL; in cdce925_pll_set_rate()
178 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); in cdce925_pll_set_rate()
183 /* calculate p = max(0, 4 - int(log2 (n/m))) */
194 --p; in cdce925_pll_calc_p()
202 struct clk *parent = clk_get_parent(hw->clk); in cdce925_pll_calc_range_bits()
220 u16 n = data->n; in cdce925_pll_prepare()
221 u16 m = data->m; in cdce925_pll_prepare()
226 u8 pll[4]; /* Bits are spread out over 4 byte registers */ in cdce925_pll_prepare()
227 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_prepare()
232 regmap_update_bits(data->chip->regmap, in cdce925_pll_prepare()
236 /* p = max(0, 4 - int(log2 (n/m))) */ in cdce925_pll_prepare()
244 return -EINVAL; in cdce925_pll_prepare()
246 r = nn - (m*q); in cdce925_pll_prepare()
249 return -EINVAL; in cdce925_pll_prepare()
261 regmap_write(data->chip->regmap, in cdce925_pll_prepare()
264 regmap_update_bits(data->chip->regmap, in cdce925_pll_prepare()
274 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_unprepare()
276 regmap_update_bits(data->chip->regmap, in cdce925_pll_unprepare()
291 switch (data->index) { in cdce925_clk_set_pdiv()
293 regmap_update_bits(data->chip->regmap, in cdce925_clk_set_pdiv()
296 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); in cdce925_clk_set_pdiv()
299 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); in cdce925_clk_set_pdiv()
302 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); in cdce925_clk_set_pdiv()
305 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); in cdce925_clk_set_pdiv()
308 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); in cdce925_clk_set_pdiv()
311 regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv); in cdce925_clk_set_pdiv()
314 regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv); in cdce925_clk_set_pdiv()
317 regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv); in cdce925_clk_set_pdiv()
320 regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv); in cdce925_clk_set_pdiv()
327 switch (data->index) { in cdce925_clk_activate()
329 regmap_update_bits(data->chip->regmap, in cdce925_clk_activate()
334 regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03); in cdce925_clk_activate()
338 regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); in cdce925_clk_activate()
342 regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03); in cdce925_clk_activate()
346 regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03); in cdce925_clk_activate()
355 cdce925_clk_set_pdiv(data, data->pdiv); in cdce925_clk_prepare()
373 if (data->pdiv) in cdce925_clk_recalc_rate()
374 return parent_rate / data->pdiv; in cdce925_clk_recalc_rate()
398 struct clk *pll = clk_get_parent(hw->clk); in cdce925_clk_best_parent_rate()
426 rate_error = abs((long)actual_rate - (long)rate); in cdce925_clk_best_parent_rate()
460 data->pdiv = cdce925_calc_divider(rate, parent_rate); in cdce925_clk_set_rate()
485 if (divider > 0x3FF) /* Y1 has 10-bit divider */ in cdce925_y1_calc_divider()
507 data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); in cdce925_clk_y1_set_rate()
532 return -ENOTSUPP; in cdce925_regmap_i2c_write()
538 dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count, in cdce925_regmap_i2c_write()
547 return -EIO; in cdce925_regmap_i2c_write()
560 return -ENOTSUPP; in cdce925_regmap_i2c_read()
562 xfer[0].addr = i2c->addr; in cdce925_regmap_i2c_read()
576 xfer[1].addr = i2c->addr; in cdce925_regmap_i2c_read()
581 ret = i2c_transfer(i2c->adapter, xfer, 2); in cdce925_regmap_i2c_read()
583 dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__, in cdce925_regmap_i2c_read()
589 return -EIO; in cdce925_regmap_i2c_read()
596 unsigned int idx = clkspec->args[0]; in of_clk_cdce925_get()
598 if (idx >= ARRAY_SIZE(data->clk)) { in of_clk_cdce925_get()
600 return ERR_PTR(-EINVAL); in of_clk_cdce925_get()
603 return &data->clk[idx].hw; in of_clk_cdce925_get()
641 struct device_node *node = client->dev.of_node; in cdce925_probe()
657 dev_dbg(&client->dev, "%s\n", __func__); in cdce925_probe()
659 err = cdce925_regulator_enable(&client->dev, "vdd"); in cdce925_probe()
663 err = cdce925_regulator_enable(&client->dev, "vddout"); in cdce925_probe()
667 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); in cdce925_probe()
669 return -ENOMEM; in cdce925_probe()
671 data->i2c_client = client; in cdce925_probe()
672 data->chip_info = &clk_cdce925_chip_info_tbl[id->driver_data]; in cdce925_probe()
674 data->chip_info->num_plls * 0x10 - 1; in cdce925_probe()
675 data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, in cdce925_probe()
676 &client->dev, &config); in cdce925_probe()
677 if (IS_ERR(data->regmap)) { in cdce925_probe()
678 dev_err(&client->dev, "failed to allocate register map\n"); in cdce925_probe()
679 return PTR_ERR(data->regmap); in cdce925_probe()
685 dev_err(&client->dev, "missing parent clock\n"); in cdce925_probe()
686 return -ENODEV; in cdce925_probe()
688 dev_dbg(&client->dev, "parent is: %s\n", parent_name); in cdce925_probe()
690 if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) in cdce925_probe()
691 regmap_write(data->regmap, in cdce925_probe()
694 regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); in cdce925_probe()
697 regmap_update_bits(data->regmap, 0x02, BIT(7), 0); in cdce925_probe()
705 for (i = 0; i < data->chip_info->num_plls; ++i) { in cdce925_probe()
707 client->dev.of_node, i); in cdce925_probe()
709 err = -ENOMEM; in cdce925_probe()
713 data->pll[i].chip = data; in cdce925_probe()
714 data->pll[i].hw.init = &init; in cdce925_probe()
715 data->pll[i].index = i; in cdce925_probe()
716 err = devm_clk_hw_register(&client->dev, &data->pll[i].hw); in cdce925_probe()
718 dev_err(&client->dev, "Failed register PLL %d\n", i); in cdce925_probe()
726 "clock-frequency", &value)) { in cdce925_probe()
727 err = clk_set_rate(data->pll[i].hw.clk, value); in cdce925_probe()
729 dev_err(&client->dev, in cdce925_probe()
734 "spread-spectrum", &value)) { in cdce925_probe()
736 "spread-spectrum-center") ? 0x80 : 0x00; in cdce925_probe()
737 regmap_update_bits(data->regmap, in cdce925_probe()
740 regmap_update_bits(data->regmap, in cdce925_probe()
752 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node); in cdce925_probe()
754 err = -ENOMEM; in cdce925_probe()
757 data->clk[0].chip = data; in cdce925_probe()
758 data->clk[0].hw.init = &init; in cdce925_probe()
759 data->clk[0].index = 0; in cdce925_probe()
760 data->clk[0].pdiv = 1; in cdce925_probe()
761 err = devm_clk_hw_register(&client->dev, &data->clk[0].hw); in cdce925_probe()
764 dev_err(&client->dev, "clock registration Y1 failed\n"); in cdce925_probe()
772 for (i = 1; i < data->chip_info->num_outputs; ++i) { in cdce925_probe()
774 client->dev.of_node, i+1); in cdce925_probe()
776 err = -ENOMEM; in cdce925_probe()
779 data->clk[i].chip = data; in cdce925_probe()
780 data->clk[i].hw.init = &init; in cdce925_probe()
781 data->clk[i].index = i; in cdce925_probe()
782 data->clk[i].pdiv = 1; in cdce925_probe()
805 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); in cdce925_probe()
808 dev_err(&client->dev, "clock registration failed\n"); in cdce925_probe()
814 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get, in cdce925_probe()
817 dev_err(&client->dev, "unable to add OF clock provider\n"); in cdce925_probe()
822 for (i = 0; i < data->chip_info->num_plls; ++i) in cdce925_probe()