1 // SPDX-License-Identifier: GPL-2.0-only
4  * Copyright (C) 2007-2012 ST-Ericsson AB
12 #include <linux/clk-provider.h>
15 #include <linux/platform_data/clk-u300.h>
33 /* Reset lines for SLOW devices 16bit (R/W) */
45 /* Reset lines for FAST devices 16bit (R/W) */
55 /* Reset lines for the rest of the peripherals 16bit (R/W) */
109 /* Single block clock enable 16bit (-/W) */
144 /* Single block clock disable 16bit (-/W) */
184 /* Reset Out 16bit (R/W) */
289 /* SC_PLL_IRQ_STATUS 16 bit (R/-) */
296 /* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
361  * NOTE: the idea is NOT to show how the clocks are routed on the chip!
363  * hierarchy has to be on in order for another clock to be on. Now,
364  * both CPU and DMA can actually be on top of the hierarchy, and that
365  * is not modeled currently. Instead we have the backbone AMBA bus on
370  * the hw itself can turn on/off or change the rate of the clock when
375  *  +- CPU
376  *  +- FSMC NANDIF NAND Flash interface
377  *  +- SEMI Shared Memory interface
378  *  +- ISP Image Signal Processor (U335 only)
379  *  +- CDS (U335 only)
380  *  +- DMA Direct Memory Access Controller
381  *  +- AAIF APP/ACC Interface (Mobile Scalable Link, MSL)
382  *  +- APEX
383  *  +- VIDEO_ENC AVE2/3 Video Encoder
384  *  +- XGAM Graphics Accelerator Controller
385  *  +- AHB
387  *  +- ahb:0 AHB Bridge
389  *  |  +- ahb:1 INTCON Interrupt controller
390  *  |  +- ahb:3 MSPRO  Memory Stick Pro controller
391  *  |  +- ahb:4 EMIF   External Memory interface
393  *  +- fast:0 FAST bridge
395  *  |  +- fast:1 MMCSD MMC/SD card reader controller
396  *  |  +- fast:2 I2S0  PCM I2S channel 0 controller
397  *  |  +- fast:3 I2S1  PCM I2S channel 1 controller
398  *  |  +- fast:4 I2C0  I2C channel 0 controller
399  *  |  +- fast:5 I2C1  I2C channel 1 controller
400  *  |  +- fast:6 SPI   SPI controller
401  *  |  +- fast:7 UART1 Secondary UART (U335 only)
403  *  +- slow:0 SLOW bridge
405  *     +- slow:1 SYSCON (not possible to control)
406  *     +- slow:2 WDOG Watchdog
407  *     +- slow:3 UART0 primary UART
408  *     +- slow:4 TIMER_APP Application timer - used in Linux
409  *     +- slow:5 KEYPAD controller
410  *     +- slow:6 GPIO controller
411  *     +- slow:7 RTC controller
412  *     +- slow:8 BT Bus Tracer (not used currently)
413  *     +- slow:9 EH Event Handler (not used currently)
414  *     +- slow:a TIMER_ACC Access style timer (not used currently)
415  *     +- slow:b PPM (U335 only, what is that?)
422  * struct clk_syscon - U300 syscon clock
426  * @reset: state holder, whether this block's reset line is asserted or not
427  * @res_reg: reset line enable/disable flag register
428  * @res_bit: bit for resetting or taking this consumer out of reset
437 	bool reset;  member
450  * Reset control functions. We remember if a block has been
451  * taken out of reset and don't remove the reset assertion again
461 	if (!sclk->res_reg)  in syscon_block_reset_enable()
464 	val = readw(sclk->res_reg);  in syscon_block_reset_enable()
465 	val |= BIT(sclk->res_bit);  in syscon_block_reset_enable()
466 	writew(val, sclk->res_reg);  in syscon_block_reset_enable()
468 	sclk->reset = true;  in syscon_block_reset_enable()
477 	if (!sclk->res_reg)  in syscon_block_reset_disable()
480 	val = readw(sclk->res_reg);  in syscon_block_reset_disable()
481 	val &= ~BIT(sclk->res_bit);  in syscon_block_reset_disable()
482 	writew(val, sclk->res_reg);  in syscon_block_reset_disable()
484 	sclk->reset = false;  in syscon_block_reset_disable()
491 	/* If the block is in reset, bring it out */  in syscon_clk_prepare()
492 	if (sclk->reset)  in syscon_clk_prepare()
501 	/* Please don't force the console into reset */  in syscon_clk_unprepare()
502 	if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)  in syscon_clk_unprepare()
504 	/* When unpreparing, force block into reset */  in syscon_clk_unprepare()
505 	if (!sclk->reset)  in syscon_clk_unprepare()
514 	if (sclk->hw_ctrld)  in syscon_clk_enable()
517 	if (sclk->clk_val == 0xFFFFU)  in syscon_clk_enable()
520 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER);  in syscon_clk_enable()
529 	if (sclk->hw_ctrld)  in syscon_clk_disable()
531 	if (sclk->clk_val == 0xFFFFU)  in syscon_clk_disable()
534 	if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN)  in syscon_clk_disable()
537 	writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR);  in syscon_clk_disable()
545 	/* If no enable register defined, it's always-on */  in syscon_clk_is_enabled()
546 	if (!sclk->en_reg)  in syscon_clk_is_enabled()
549 	val = readw(sclk->en_reg);  in syscon_clk_is_enabled()
550 	val &= BIT(sclk->en_bit);  in syscon_clk_is_enabled()
571 	switch (sclk->clk_val) {  in syscon_clk_recalc_rate()
638 	if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)  in syscon_clk_round_rate()
657 	if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN)  in syscon_clk_set_rate()
658 		return -EINVAL;  in syscon_clk_set_rate()
673 		return -EINVAL;  in syscon_clk_set_rate()
702 	struct clk_init_data init;  in syscon_clk_register()  local
707 		return ERR_PTR(-ENOMEM);  in syscon_clk_register()
709 	init.name = name;  in syscon_clk_register()
710 	init.ops = &syscon_clk_ops;  in syscon_clk_register()
711 	init.flags = flags;  in syscon_clk_register()
712 	init.parent_names = (parent_name ? &parent_name : NULL);  in syscon_clk_register()
713 	init.num_parents = (parent_name ? 1 : 0);  in syscon_clk_register()
714 	sclk->hw.init = &init;  in syscon_clk_register()
715 	sclk->hw_ctrld = hw_ctrld;  in syscon_clk_register()
716 	/* Assume the block is in reset at registration */  in syscon_clk_register()
717 	sclk->reset = true;  in syscon_clk_register()
718 	sclk->res_reg = res_reg;  in syscon_clk_register()
719 	sclk->res_bit = res_bit;  in syscon_clk_register()
720 	sclk->en_reg = en_reg;  in syscon_clk_register()
721 	sclk->en_bit = en_bit;  in syscon_clk_register()
722 	sclk->clk_val = clk_val;  in syscon_clk_register()
724 	hw = &sclk->hw;  in syscon_clk_register()
739  * struct u300_clock - defines the bits and pieces for a certain clock
743  * @clk_val: a value to poke in the one-write enable/disable registers
799 		/* INTCON: cannot be enabled, just taken out of reset */
854 		/* No clock enable register bit */
873 	struct clk_hw *hw = ERR_PTR(-EINVAL);  in of_u300_syscon_clk_init()
874 	const char *clk_name = np->name;  in of_u300_syscon_clk_init()
882 	if (of_property_read_u32(np, "clock-type", &clk_type)) {  in of_u300_syscon_clk_init()
883 		pr_err("%s: syscon clock \"%s\" missing clock-type property\n",  in of_u300_syscon_clk_init()
887 	if (of_property_read_u32(np, "clock-id", &clk_id)) {  in of_u300_syscon_clk_init()
888 		pr_err("%s: syscon clock \"%s\" missing clock-id property\n",  in of_u300_syscon_clk_init()
915 		if (u3clk->type == clk_type && u3clk->id == clk_id)  in of_u300_syscon_clk_init()
917 						 0, u3clk->hw_ctrld,  in of_u300_syscon_clk_init()
918 						 res_reg, u3clk->id,  in of_u300_syscon_clk_init()
919 						 en_reg, u3clk->id,  in of_u300_syscon_clk_init()
920 						 u3clk->clk_val);  in of_u300_syscon_clk_init()
927 		 * Some few system clocks - device tree does not  in of_u300_syscon_clk_init()
941  * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
957 	/* The MMC and MSPRO clocks need some special set-up */  in mclk_clk_prepare()
958 	if (!mclk->is_mspro) {  in mclk_clk_prepare()
989 		 * on 13 MHz PLL used for RTC etc kicks into use  in mclk_clk_recalc_rate()
1000 		 * divided in two nybbles, bit 7-4 gives cycles-1 to count  in mclk_clk_recalc_rate()
1001 		 * high, bit 3-0 gives cycles-1 to count low. Distribute  in mclk_clk_recalc_rate()
1002 		 * these with no more than 1 cycle difference between  in mclk_clk_recalc_rate()
1099 		return -EINVAL;  in mclk_clk_set_rate()
1121 	struct clk_init_data init;  in mclk_clk_register()  local
1126 		return ERR_PTR(-ENOMEM);  in mclk_clk_register()
1128 	init.name = "mclk";  in mclk_clk_register()
1129 	init.ops = &mclk_ops;  in mclk_clk_register()
1130 	init.flags = 0;  in mclk_clk_register()
1131 	init.parent_names = (parent_name ? &parent_name : NULL);  in mclk_clk_register()
1132 	init.num_parents = (parent_name ? 1 : 0);  in mclk_clk_register()
1133 	mclk->hw.init = &init;  in mclk_clk_register()
1134 	mclk->is_mspro = is_mspro;  in mclk_clk_register()
1136 	hw = &mclk->hw;  in mclk_clk_register()
1149 	const char *clk_name = np->name;  in of_u300_syscon_mclk_init()
1160 		.compatible = "fixed-clock",
1164 		.compatible = "fixed-factor-clock",
1168 		.compatible = "stericsson,u300-syscon-clk",
1172 		.compatible = "stericsson,u300-syscon-mclk",