Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
13 #include "clk-regmap.h"
14 #include "clk-pll.h"
15 #include "clk-mpll.h"
16 #include "meson-eeclk.h"
17 #include "vid-pll-div.h"
86 .data = &(struct meson_clk_pll_data){
89 .shift = 30,
94 .shift = 0,
99 .shift = 9,
104 .shift = 0,
109 .shift = 31,
114 .shift = 29,
129 .data = &(struct clk_regmap_div_data){
131 .shift = 16,
163 .data = &(struct meson_clk_pll_data){
166 .shift = 30,
171 .shift = 0,
176 .shift = 9,
181 .shift = 0,
186 .shift = 31,
191 .shift = 28,
211 .data = &(struct meson_clk_pll_data){
214 .shift = 30,
219 .shift = 0,
224 .shift = 9,
228 * On gxl, there is a register shift due to
235 .shift = 0,
240 .shift = 31,
245 .shift = 28,
265 .data = &(struct clk_regmap_div_data){
267 .shift = 16,
283 .data = &(struct clk_regmap_div_data){
285 .shift = 22,
301 .data = &(struct clk_regmap_div_data){
303 .shift = 18,
319 .data = &(struct clk_regmap_div_data){
321 .shift = 21,
337 .data = &(struct clk_regmap_div_data){
339 .shift = 23,
355 .data = &(struct clk_regmap_div_data){
357 .shift = 19,
373 .data = &(struct meson_clk_pll_data){
376 .shift = 30,
381 .shift = 0,
386 .shift = 9,
391 .shift = 31,
396 .shift = 29,
411 .data = &(struct clk_regmap_div_data){
413 .shift = 10,
435 .data = &(struct meson_clk_pll_data){
438 .shift = 30,
443 .shift = 0,
448 .shift = 9,
453 .shift = 31,
458 .shift = 29,
484 .data = &(struct meson_clk_pll_data){
487 .shift = 30,
492 .shift = 0,
497 .shift = 9,
502 .shift = 0,
507 .shift = 31,
512 .shift = 29,
530 .data = &(struct clk_regmap_div_data){
532 .shift = 16,
548 .index = -1,
569 .data = &(struct clk_regmap_gate_data){
596 .data = &(struct clk_regmap_gate_data){
615 * b) CCF has a clock hand-off mechanism to make the sure the
634 .data = &(struct clk_regmap_gate_data){
660 .data = &(struct clk_regmap_gate_data){
686 .data = &(struct clk_regmap_gate_data){
701 .data = &(struct clk_regmap_div_data){
703 .shift = 12,
715 .data = &(struct meson_clk_mpll_data){
718 .shift = 0,
723 .shift = 25,
728 .shift = 16,
744 .data = &(struct meson_clk_mpll_data){
747 .shift = 0,
752 .shift = 15,
757 .shift = 16,
773 .data = &(struct clk_regmap_gate_data){
788 .index = -1,
796 .data = &(struct meson_clk_mpll_data){
799 .shift = 0,
804 .shift = 15,
809 .shift = 16,
825 .data = &(struct clk_regmap_gate_data){
839 .data = &(struct meson_clk_mpll_data){
842 .shift = 0,
847 .shift = 15,
852 .shift = 16,
868 .data = &(struct clk_regmap_gate_data){
893 .data = &(struct clk_regmap_mux_data){
896 .shift = 12,
913 .data = &(struct clk_regmap_div_data){
915 .shift = 0,
930 .data = &(struct clk_regmap_gate_data){
946 .data = &(struct clk_regmap_mux_data){
949 .shift = 9,
964 .data = &(struct clk_regmap_div_data){
966 .shift = 0,
981 .data = &(struct clk_regmap_gate_data){
998 * muxed by a glitch-free switch. The CCF can manage this glitch-free
999 * mux because it does top-to-bottom updates the each clock tree and
1015 .data = &(struct clk_regmap_mux_data){
1018 .shift = 9,
1036 .data = &(struct clk_regmap_div_data){
1038 .shift = 0,
1053 .data = &(struct clk_regmap_gate_data){
1069 .data = &(struct clk_regmap_mux_data){
1072 .shift = 25,
1090 .data = &(struct clk_regmap_div_data){
1092 .shift = 16,
1107 .data = &(struct clk_regmap_gate_data){
1128 .data = &(struct clk_regmap_mux_data){
1131 .shift = 31,
1143 .data = &(struct clk_regmap_mux_data){
1146 .shift = 9,
1163 .data = &(struct clk_regmap_div_data) {
1165 .shift = 0,
1181 .data = &(struct clk_regmap_gate_data){
1197 .data = &(struct clk_regmap_mux_data){
1200 .shift = 25,
1217 .data = &(struct clk_regmap_div_data){
1219 .shift = 16,
1235 .data = &(struct clk_regmap_gate_data){
1251 .data = &(struct clk_regmap_mux_data){
1254 .shift = 27,
1265 *The parent is specific to origin of the audio data. Let the
1279 { .name = "cts_slow_oscin", .index = -1 },
1285 .data = &(struct clk_regmap_mux_data){
1288 .shift = 16,
1300 .data = &(struct clk_regmap_div_data){
1302 .shift = 0,
1317 .data = &(struct clk_regmap_gate_data){
1348 .data = &(struct clk_regmap_mux_data){
1351 .shift = 9,
1363 .data = &(struct clk_regmap_div_data){
1365 .shift = 0,
1381 .data = &(struct clk_regmap_gate_data){
1398 .data = &(struct clk_regmap_mux_data){
1401 .shift = 25,
1413 .data = &(struct clk_regmap_div_data){
1415 .shift = 16,
1431 .data = &(struct clk_regmap_gate_data){
1448 .data = &(struct clk_regmap_mux_data){
1451 .shift = 9,
1463 .data = &(struct clk_regmap_div_data){
1465 .shift = 0,
1481 .data = &(struct clk_regmap_gate_data){
1506 .data = &(struct clk_regmap_mux_data){
1509 .shift = 9,
1525 .data = &(struct clk_regmap_div_data){
1527 .shift = 0,
1540 .data = &(struct clk_regmap_gate_data){
1554 .data = &(struct clk_regmap_mux_data){
1557 .shift = 25,
1573 .data = &(struct clk_regmap_div_data){
1575 .shift = 16,
1588 .data = &(struct clk_regmap_gate_data){
1602 .data = &(struct clk_regmap_mux_data){
1605 .shift = 31,
1633 .data = &(struct clk_regmap_mux_data){
1636 .shift = 9,
1652 .data = &(struct clk_regmap_div_data){
1654 .shift = 0,
1669 .data = &(struct clk_regmap_gate_data){
1685 .data = &(struct clk_regmap_mux_data){
1688 .shift = 25,
1704 .data = &(struct clk_regmap_div_data){
1706 .shift = 16,
1721 .data = &(struct clk_regmap_gate_data){
1737 .data = &(struct clk_regmap_mux_data){
1740 .shift = 31,
1759 .data = &(struct clk_regmap_gate_data){
1775 .data = &(struct meson_vid_pll_div_data){
1778 .shift = 0,
1783 .shift = 16,
1799 .index = -1,
1815 { .name = "hdmi_pll", .index = -1 },
1819 .data = &(struct clk_regmap_mux_data){
1822 .shift = 18,
1838 .data = &(struct clk_regmap_gate_data){
1864 .data = &(struct clk_regmap_mux_data){
1867 .shift = 16,
1884 .data = &(struct clk_regmap_mux_data){
1887 .shift = 16,
1904 .data = &(struct clk_regmap_gate_data){
1918 .data = &(struct clk_regmap_gate_data){
1932 .data = &(struct clk_regmap_div_data){
1934 .shift = 0,
1949 .data = &(struct clk_regmap_div_data){
1951 .shift = 0,
1966 .data = &(struct clk_regmap_gate_data){
1980 .data = &(struct clk_regmap_gate_data){
1994 .data = &(struct clk_regmap_gate_data){
2008 .data = &(struct clk_regmap_gate_data){
2022 .data = &(struct clk_regmap_gate_data){
2036 .data = &(struct clk_regmap_gate_data){
2050 .data = &(struct clk_regmap_gate_data){
2064 .data = &(struct clk_regmap_gate_data){
2078 .data = &(struct clk_regmap_gate_data){
2092 .data = &(struct clk_regmap_gate_data){
2106 .data = &(struct clk_regmap_gate_data){
2120 .data = &(struct clk_regmap_gate_data){
2252 .data = &(struct clk_regmap_mux_data){
2255 .shift = 28,
2268 .data = &(struct clk_regmap_mux_data){
2271 .shift = 20,
2284 .data = &(struct clk_regmap_mux_data){
2287 .shift = 28,
2315 .data = &(struct clk_regmap_mux_data){
2318 .shift = 16,
2337 .data = &(struct clk_regmap_gate_data){
2353 .data = &(struct clk_regmap_gate_data){
2369 .data = &(struct clk_regmap_gate_data){
2385 .data = &(struct clk_regmap_gate_data){
2410 .data = &(struct clk_regmap_mux_data){
2413 .shift = 9,
2426 .data = &(struct clk_regmap_div_data){
2428 .shift = 0,
2441 .data = &(struct clk_regmap_gate_data){
2464 .data = &(struct clk_regmap_mux_data){
2467 .shift = 9,
2480 .data = &(struct clk_regmap_div_data){
2482 .shift = 0,
2498 .data = &(struct clk_regmap_gate_data){
2514 .data = &(struct clk_regmap_mux_data){
2517 .shift = 25,
2530 .data = &(struct clk_regmap_div_data){
2532 .shift = 16,
2548 .data = &(struct clk_regmap_gate_data){
2580 .data = &(struct clk_regmap_mux_data){
2583 .shift = 12,
2601 .data = &(struct clk_regmap_div_data){
2603 .shift = 0,
2618 .data = &(struct clk_regmap_gate_data){
3556 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3557 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3564 .name = "gxbb-clkc",