1 // SPDX-License-Identifier: GPL-2.0+
3  * Marvell Armada AP CPU Clock Controller
11 #define pr_fmt(fmt) "ap-cpu-clk: " fmt
13 #include <linux/clk-provider.h>
34  * struct cpu_dfs_regs: CPU DFS register mapping
35  * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
54 /* AP806 CPU DFS register mapping*/
92 /* AP807 CPU DFS register mapping */
128  * struct ap806_clk: CPU cluster clock controller instance
129  * @cluster: Cluster clock controller index
130  * @clk_name: Cluster clock controller name
131  * @dev : Cluster clock device
132  * @hw: HW specific structure of Cluster clock controller
136 	unsigned int cluster;  member
151 	cpu_clkdiv_reg = clk->pll_regs->divider_reg +  in ap_cpu_clk_recalc_rate()
152 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_recalc_rate()
153 	regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio);  in ap_cpu_clk_recalc_rate()
154 	cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;  in ap_cpu_clk_recalc_rate()
155 	cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;  in ap_cpu_clk_recalc_rate()
167 	cpu_clkdiv_reg = clk->pll_regs->divider_reg +  in ap_cpu_clk_set_rate()
168 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_set_rate()
169 	cpu_force_reg = clk->pll_regs->force_reg +  in ap_cpu_clk_set_rate()
170 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_set_rate()
171 	cpu_ratio_reg = clk->pll_regs->ratio_reg +  in ap_cpu_clk_set_rate()
172 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_set_rate()
174 	regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &reg);  in ap_cpu_clk_set_rate()
175 	reg &= ~(clk->pll_regs->divider_mask);  in ap_cpu_clk_set_rate()
176 	reg |= (divider << clk->pll_regs->divider_offset);  in ap_cpu_clk_set_rate()
179 	 * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio  in ap_cpu_clk_set_rate()
182 	if (clk->pll_regs->divider_ratio) {  in ap_cpu_clk_set_rate()
184 		reg |= ((divider * clk->pll_regs->divider_ratio) <<  in ap_cpu_clk_set_rate()
187 	regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg);  in ap_cpu_clk_set_rate()
190 	regmap_update_bits(clk->pll_cr_base, cpu_force_reg,  in ap_cpu_clk_set_rate()
191 			   clk->pll_regs->force_mask,  in ap_cpu_clk_set_rate()
192 			   clk->pll_regs->force_mask);  in ap_cpu_clk_set_rate()
194 	regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,  in ap_cpu_clk_set_rate()
195 			   BIT(clk->pll_regs->ratio_offset),  in ap_cpu_clk_set_rate()
196 			   BIT(clk->pll_regs->ratio_offset));  in ap_cpu_clk_set_rate()
198 	stable_bit = BIT(clk->pll_regs->ratio_state_offset +  in ap_cpu_clk_set_rate()
199 			 clk->cluster *  in ap_cpu_clk_set_rate()
200 			 clk->pll_regs->ratio_state_cluster_offset);  in ap_cpu_clk_set_rate()
201 	ret = regmap_read_poll_timeout(clk->pll_cr_base,  in ap_cpu_clk_set_rate()
202 				       clk->pll_regs->ratio_state_reg, reg,  in ap_cpu_clk_set_rate()
208 	regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,  in ap_cpu_clk_set_rate()
209 			   BIT(clk->pll_regs->ratio_offset), 0);  in ap_cpu_clk_set_rate()
233 	struct device *dev = &pdev->dev;  in ap_cpu_clock_probe()
234 	struct device_node *dn, *np = dev->of_node;  in ap_cpu_clock_probe()
239 	regmap = syscon_node_to_regmap(np->parent);  in ap_cpu_clock_probe()
246 	 * AP806 has 4 cpus and DFS for AP806 is controlled per  in ap_cpu_clock_probe()
247 	 * cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to  in ap_cpu_clock_probe()
249 	 * they are enabled or not.  Since cpu0 is the boot cpu, then  in ap_cpu_clock_probe()
251 	 * will exist and the cluster number is 2; otherwise the  in ap_cpu_clock_probe()
252 	 * cluster number is 1.  in ap_cpu_clock_probe()
256 		int cpu, err;  in ap_cpu_clock_probe()  local
258 		err = of_property_read_u32(dn, "reg", &cpu);  in ap_cpu_clock_probe()
265 		if (cpu & APN806_CLUSTER_NUM_MASK) {  in ap_cpu_clock_probe()
272 	 * DFS for AP806 is controlled per cluster (2 CPUs per cluster),  in ap_cpu_clock_probe()
273 	 * so allocate structs per cluster  in ap_cpu_clock_probe()
278 		return -ENOMEM;  in ap_cpu_clock_probe()
284 		return -ENOMEM;  in ap_cpu_clock_probe()
287 		char *clk_name = "cpu-cluster-0";  in ap_cpu_clock_probe()
291 		int cpu, err;  in ap_cpu_clock_probe()  local
293 		err = of_property_read_u32(dn, "reg", &cpu);  in ap_cpu_clock_probe()
299 		cluster_index = cpu & APN806_CLUSTER_NUM_MASK;  in ap_cpu_clock_probe()
302 		/* Initialize once for one cluster */  in ap_cpu_clock_probe()
303 		if (ap_cpu_data->hws[cluster_index])  in ap_cpu_clock_probe()
310 			return -EINVAL;  in ap_cpu_clock_probe()
315 			ap_cp_unique_name(dev, np->parent, clk_name);  in ap_cpu_clock_probe()
316 		ap_cpu_clk[cluster_index].cluster = cluster_index;  in ap_cpu_clock_probe()
320 		ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);  in ap_cpu_clock_probe()
332 		ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index].hw;  in ap_cpu_clock_probe()
335 	ap_cpu_data->num = cluster_index + 1;  in ap_cpu_clock_probe()
346 		.compatible = "marvell,ap806-cpu-clock",
350 		.compatible = "marvell,ap807-cpu-clock",
359 		.name	= "marvell-ap-cpu-clock",