1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
22 #include "clk-regmap.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
26 #include "clk-regmap-divider.h"
46  * struct clk_fepll_vco - vco feedback divider corresponds for FEPLL clocks
62  * struct clk_fepll - clk divider corresponds to FEPLL clocks
1213 	const struct clk_fepll_vco *pll_vco = pll_div->pll_vco;  in clk_fepll_vco_calc_rate()
1217 	regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv);  in clk_fepll_vco_calc_rate()
1218 	refclkdiv = (cdiv >> pll_vco->refclkdiv_shift) &  in clk_fepll_vco_calc_rate()
1219 		    (BIT(pll_vco->refclkdiv_width) - 1);  in clk_fepll_vco_calc_rate()
1220 	fdbkdiv = (cdiv >> pll_vco->fdbkdiv_shift) &  in clk_fepll_vco_calc_rate()
1221 		  (BIT(pll_vco->fdbkdiv_width) - 1);  in clk_fepll_vco_calc_rate()
1258 	f = qcom_find_freq(pll->freq_tbl, rate);  in clk_cpu_div_round_rate()
1260 		return -EINVAL;  in clk_cpu_div_round_rate()
1262 	p_hw = clk_hw_get_parent_by_index(hw, f->src);  in clk_cpu_div_round_rate()
1265 	return f->freq;  in clk_cpu_div_round_rate()
1281 	f = qcom_find_freq(pll->freq_tbl, rate);  in clk_cpu_div_set_rate()
1283 		return -EINVAL;  in clk_cpu_div_set_rate()
1285 	mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift;  in clk_cpu_div_set_rate()
1286 	ret = regmap_update_bits(pll->cdiv.clkr.regmap,  in clk_cpu_div_set_rate()
1287 				 pll->cdiv.reg, mask,  in clk_cpu_div_set_rate()
1288 				 f->pre_div << pll->cdiv.shift);  in clk_cpu_div_set_rate()
1312 	regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);  in clk_cpu_div_recalc_rate()
1313 	cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);  in clk_cpu_div_recalc_rate()
1389 	if (pll->fixed_div) {  in clk_regmap_clk_div_recalc_rate()
1390 		pre_div = pll->fixed_div;  in clk_regmap_clk_div_recalc_rate()
1392 		regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);  in clk_regmap_clk_div_recalc_rate()
1393 		cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);  in clk_regmap_clk_div_recalc_rate()
1395 		for (clkt = pll->div_table; clkt->div; clkt++) {  in clk_regmap_clk_div_recalc_rate()
1396 			if (clkt->val == cdiv)  in clk_regmap_clk_div_recalc_rate()
1397 				pre_div = clkt->div;  in clk_regmap_clk_div_recalc_rate()
1730 	{ .compatible = "qcom,gcc-ipq4019" },
1774 		.name	= "qcom,gcc-ipq4019",
1791 MODULE_ALIAS("platform:gcc-ipq4019");
1793 MODULE_DESCRIPTION("QCOM GCC IPQ4019 driver");