Lines Matching +full:0 +full:x50004
37 .offset = 0x0,
40 .enable_reg = 0x52010,
41 .enable_mask = BIT(0),
55 { 0x1, 2 },
60 .offset = 0x0,
90 .offset = 0x01000,
93 .enable_reg = 0x52010,
108 .offset = 0x76000,
111 .enable_reg = 0x52010,
126 .offset = 0x13000,
129 .enable_reg = 0x52010,
144 .offset = 0x27000,
147 .enable_reg = 0x52010,
162 { P_BI_TCXO, 0 },
183 { P_BI_TCXO, 0 },
199 { P_BI_TCXO, 0 },
217 { P_BI_TCXO, 0 },
229 { P_BI_TCXO, 0 },
245 { P_BI_TCXO, 0 },
261 { P_BI_TCXO, 0 },
275 F(19200000, P_BI_TCXO, 1, 0, 0),
280 .cmd_rcgr = 0x48014,
281 .mnd_width = 0,
295 F(19200000, P_BI_TCXO, 1, 0, 0),
296 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
297 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
298 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
299 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
304 .cmd_rcgr = 0x64004,
318 .cmd_rcgr = 0x65004,
332 .cmd_rcgr = 0x66004,
346 F(19200000, P_BI_TCXO, 1, 0, 0),
347 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
352 .cmd_rcgr = 0x33010,
353 .mnd_width = 0,
366 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
367 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
368 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
373 .cmd_rcgr = 0x4b00c,
374 .mnd_width = 0,
389 F(19200000, P_BI_TCXO, 1, 0, 0),
393 F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
395 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
398 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
402 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
403 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
415 .cmd_rcgr = 0x17034,
431 .cmd_rcgr = 0x17164,
447 .cmd_rcgr = 0x17294,
463 .cmd_rcgr = 0x173c4,
479 .cmd_rcgr = 0x174f4,
495 .cmd_rcgr = 0x17624,
511 .cmd_rcgr = 0x18018,
527 .cmd_rcgr = 0x18148,
543 .cmd_rcgr = 0x18278,
559 .cmd_rcgr = 0x183a8,
575 .cmd_rcgr = 0x184d8,
591 .cmd_rcgr = 0x18608,
603 F(19200000, P_BI_TCXO, 1, 0, 0),
606 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
607 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
608 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
609 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
614 .cmd_rcgr = 0x12028,
628 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
629 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
630 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
631 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
636 .cmd_rcgr = 0x12010,
637 .mnd_width = 0,
651 F(9600000, P_BI_TCXO, 2, 0, 0),
652 F(19200000, P_BI_TCXO, 1, 0, 0),
653 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
654 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
655 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
660 .cmd_rcgr = 0x1400c,
675 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
676 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
677 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
678 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
679 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
684 .cmd_rcgr = 0x77020,
698 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
699 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
700 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
701 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
706 .cmd_rcgr = 0x77048,
707 .mnd_width = 0,
720 F(9600000, P_BI_TCXO, 2, 0, 0),
721 F(19200000, P_BI_TCXO, 1, 0, 0),
726 .cmd_rcgr = 0x77098,
727 .mnd_width = 0,
740 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
741 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
742 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
747 .cmd_rcgr = 0x77060,
748 .mnd_width = 0,
761 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
762 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
763 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
764 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
769 .cmd_rcgr = 0xf01c,
783 F(19200000, P_BI_TCXO, 1, 0, 0),
784 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
789 .cmd_rcgr = 0xf034,
790 .mnd_width = 0,
803 F(19200000, P_BI_TCXO, 1, 0, 0),
808 .cmd_rcgr = 0xf060,
809 .mnd_width = 0,
822 F(4800000, P_BI_TCXO, 4, 0, 0),
823 F(19200000, P_BI_TCXO, 1, 0, 0),
828 .cmd_rcgr = 0x3d030,
829 .mnd_width = 0,
842 .halt_reg = 0x82024,
844 .hwcg_reg = 0x82024,
847 .enable_reg = 0x82024,
848 .enable_mask = BIT(0),
862 .halt_reg = 0x8201c,
865 .enable_reg = 0x8201c,
866 .enable_mask = BIT(0),
880 .halt_reg = 0x38004,
882 .hwcg_reg = 0x38004,
885 .enable_reg = 0x52000,
895 .halt_reg = 0xb008,
897 .hwcg_reg = 0xb008,
900 .enable_reg = 0xb008,
901 .enable_mask = BIT(0),
910 .halt_reg = 0xb020,
913 .enable_reg = 0xb020,
914 .enable_mask = BIT(0),
923 .halt_reg = 0xb080,
925 .hwcg_reg = 0xb080,
928 .enable_reg = 0xb080,
929 .enable_mask = BIT(0),
938 .halt_reg = 0xb02c,
941 .enable_reg = 0xb02c,
942 .enable_mask = BIT(0),
951 .halt_reg = 0x4100c,
953 .hwcg_reg = 0x4100c,
956 .enable_reg = 0x52000,
966 .halt_reg = 0x41008,
969 .enable_reg = 0x52000,
979 .halt_reg = 0x41004,
982 .enable_reg = 0x52000,
992 .halt_reg = 0x502c,
995 .enable_reg = 0x502c,
996 .enable_mask = BIT(0),
1011 .halt_reg = 0x48000,
1014 .enable_reg = 0x52000,
1029 .halt_reg = 0x48008,
1032 .enable_reg = 0x48008,
1033 .enable_mask = BIT(0),
1042 .halt_reg = 0x4452c,
1045 .enable_reg = 0x4452c,
1046 .enable_mask = BIT(0),
1057 .enable_reg = 0x52000,
1073 .enable_reg = 0x52000,
1087 .halt_reg = 0xb024,
1090 .enable_reg = 0xb024,
1091 .enable_mask = BIT(0),
1100 .halt_reg = 0xb084,
1102 .hwcg_reg = 0xb084,
1105 .enable_reg = 0xb084,
1106 .enable_mask = BIT(0),
1115 .halt_reg = 0xb030,
1118 .enable_reg = 0xb030,
1119 .enable_mask = BIT(0),
1128 .halt_reg = 0x64000,
1131 .enable_reg = 0x64000,
1132 .enable_mask = BIT(0),
1146 .halt_reg = 0x65000,
1149 .enable_reg = 0x65000,
1150 .enable_mask = BIT(0),
1164 .halt_reg = 0x66000,
1167 .enable_reg = 0x66000,
1168 .enable_mask = BIT(0),
1184 .enable_reg = 0x52000,
1200 .enable_reg = 0x52000,
1214 .halt_reg = 0x7100c,
1217 .enable_reg = 0x7100c,
1218 .enable_mask = BIT(0),
1227 .halt_reg = 0x71018,
1230 .enable_reg = 0x71018,
1231 .enable_mask = BIT(0),
1240 .halt_reg = 0x4d008,
1243 .enable_reg = 0x4d008,
1244 .enable_mask = BIT(0),
1253 .halt_reg = 0x73008,
1256 .enable_reg = 0x73008,
1257 .enable_mask = BIT(0),
1266 .halt_reg = 0x73018,
1269 .enable_reg = 0x73018,
1270 .enable_mask = BIT(0),
1279 .halt_reg = 0x7301c,
1282 .enable_reg = 0x7301c,
1283 .enable_mask = BIT(0),
1292 .halt_reg = 0x4d004,
1294 .hwcg_reg = 0x4d004,
1297 .enable_reg = 0x4d004,
1298 .enable_mask = BIT(0),
1307 .halt_reg = 0x4d1a0,
1309 .hwcg_reg = 0x4d1a0,
1312 .enable_reg = 0x4d1a0,
1313 .enable_mask = BIT(0),
1324 .enable_reg = 0x52000,
1340 .enable_reg = 0x52000,
1355 .halt_reg = 0x3300c,
1358 .enable_reg = 0x3300c,
1359 .enable_mask = BIT(0),
1373 .halt_reg = 0x33004,
1375 .hwcg_reg = 0x33004,
1378 .enable_reg = 0x33004,
1379 .enable_mask = BIT(0),
1388 .halt_reg = 0x33008,
1391 .enable_reg = 0x33008,
1392 .enable_mask = BIT(0),
1401 .halt_reg = 0x34004,
1403 .hwcg_reg = 0x34004,
1406 .enable_reg = 0x52000,
1416 .halt_reg = 0x4b004,
1418 .hwcg_reg = 0x4b004,
1421 .enable_reg = 0x4b004,
1422 .enable_mask = BIT(0),
1431 .halt_reg = 0x4b008,
1434 .enable_reg = 0x4b008,
1435 .enable_mask = BIT(0),
1449 .halt_reg = 0x17014,
1452 .enable_reg = 0x52008,
1462 .halt_reg = 0x1700c,
1465 .enable_reg = 0x52008,
1475 .halt_reg = 0x17030,
1478 .enable_reg = 0x52008,
1493 .halt_reg = 0x17160,
1496 .enable_reg = 0x52008,
1511 .halt_reg = 0x17290,
1514 .enable_reg = 0x52008,
1529 .halt_reg = 0x173c0,
1532 .enable_reg = 0x52008,
1547 .halt_reg = 0x174f0,
1550 .enable_reg = 0x52008,
1565 .halt_reg = 0x17620,
1568 .enable_reg = 0x52008,
1583 .halt_reg = 0x18004,
1586 .enable_reg = 0x52008,
1596 .halt_reg = 0x18008,
1599 .enable_reg = 0x52008,
1609 .halt_reg = 0x18014,
1612 .enable_reg = 0x52008,
1627 .halt_reg = 0x18144,
1630 .enable_reg = 0x52008,
1645 .halt_reg = 0x18274,
1648 .enable_reg = 0x52008,
1663 .halt_reg = 0x183a4,
1666 .enable_reg = 0x52008,
1681 .halt_reg = 0x184d4,
1684 .enable_reg = 0x52008,
1699 .halt_reg = 0x18604,
1702 .enable_reg = 0x52008,
1717 .halt_reg = 0x17004,
1720 .enable_reg = 0x52008,
1730 .halt_reg = 0x17008,
1732 .hwcg_reg = 0x17008,
1735 .enable_reg = 0x52008,
1745 .halt_reg = 0x1800c,
1748 .enable_reg = 0x52008,
1758 .halt_reg = 0x18010,
1760 .hwcg_reg = 0x18010,
1763 .enable_reg = 0x52008,
1773 .halt_reg = 0x12008,
1776 .enable_reg = 0x12008,
1777 .enable_mask = BIT(0),
1786 .halt_reg = 0x1200c,
1789 .enable_reg = 0x1200c,
1790 .enable_mask = BIT(0),
1804 .halt_reg = 0x12040,
1807 .enable_reg = 0x12040,
1808 .enable_mask = BIT(0),
1822 .halt_reg = 0x14008,
1825 .enable_reg = 0x14008,
1826 .enable_mask = BIT(0),
1835 .halt_reg = 0x14004,
1838 .enable_reg = 0x14004,
1839 .enable_mask = BIT(0),
1854 .halt_reg = 0x4144,
1857 .enable_reg = 0x52000,
1858 .enable_mask = BIT(0),
1872 .halt_reg = 0x8c000,
1875 .enable_reg = 0x8c000,
1876 .enable_mask = BIT(0),
1885 .halt_reg = 0x77014,
1887 .hwcg_reg = 0x77014,
1890 .enable_reg = 0x77014,
1891 .enable_mask = BIT(0),
1900 .halt_reg = 0x77038,
1902 .hwcg_reg = 0x77038,
1905 .enable_reg = 0x77038,
1906 .enable_mask = BIT(0),
1920 .halt_reg = 0x77090,
1922 .hwcg_reg = 0x77090,
1925 .enable_reg = 0x77090,
1926 .enable_mask = BIT(0),
1940 .halt_reg = 0x77094,
1942 .hwcg_reg = 0x77094,
1945 .enable_reg = 0x77094,
1946 .enable_mask = BIT(0),
1960 .halt_reg = 0x7701c,
1963 .enable_reg = 0x7701c,
1964 .enable_mask = BIT(0),
1973 .halt_reg = 0x77018,
1976 .enable_reg = 0x77018,
1977 .enable_mask = BIT(0),
1986 .halt_reg = 0x7708c,
1988 .hwcg_reg = 0x7708c,
1991 .enable_reg = 0x7708c,
1992 .enable_mask = BIT(0),
2006 .halt_reg = 0xf010,
2009 .enable_reg = 0xf010,
2010 .enable_mask = BIT(0),
2024 .halt_reg = 0xf018,
2027 .enable_reg = 0xf018,
2028 .enable_mask = BIT(0),
2043 .halt_reg = 0xf014,
2046 .enable_reg = 0xf014,
2047 .enable_mask = BIT(0),
2056 .halt_reg = 0x8c010,
2059 .enable_reg = 0x8c010,
2060 .enable_mask = BIT(0),
2069 .halt_reg = 0xf050,
2072 .enable_reg = 0xf050,
2073 .enable_mask = BIT(0),
2087 .halt_reg = 0xf054,
2090 .enable_reg = 0xf054,
2091 .enable_mask = BIT(0),
2105 .halt_reg = 0xf058,
2108 .enable_reg = 0xf058,
2109 .enable_mask = BIT(0),
2118 .halt_reg = 0x6a004,
2120 .hwcg_reg = 0x6a004,
2123 .enable_reg = 0x6a004,
2124 .enable_mask = BIT(0),
2133 .halt_reg = 0xb01c,
2136 .enable_reg = 0xb01c,
2137 .enable_mask = BIT(0),
2148 .enable_reg = 0x52000,
2163 .halt_reg = 0xb07c,
2165 .hwcg_reg = 0xb07c,
2168 .enable_reg = 0xb07c,
2169 .enable_mask = BIT(0),
2178 .halt_reg = 0xb028,
2181 .enable_reg = 0xb028,
2182 .enable_mask = BIT(0),
2191 .halt_reg = 0x8a000,
2194 .enable_reg = 0x8a000,
2195 .enable_mask = BIT(0),
2204 .halt_reg = 0x8a004,
2207 .enable_reg = 0x8a004,
2208 .enable_mask = BIT(0),
2217 .halt_reg = 0x8a00c,
2220 .enable_reg = 0x8a00c,
2221 .enable_mask = BIT(0),
2230 .halt_reg = 0x8a150,
2233 .enable_reg = 0x8a150,
2234 .enable_mask = BIT(0),
2243 .halt_reg = 0x8a154,
2246 .enable_reg = 0x8a154,
2247 .enable_mask = BIT(0),
2256 .halt_reg = 0x47018,
2259 .enable_reg = 0x47018,
2260 .enable_mask = BIT(0),
2269 .gdscr = 0x77004,
2277 .gdscr = 0x0f004,
2285 .gdscr = 0x7d040,
2294 .gdscr = 0x7d044,
2449 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2450 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
2451 [GCC_UFS_PHY_BCR] = { 0x77000 },
2452 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2453 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2454 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
2455 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2456 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2457 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
2458 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2459 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2481 .max_register = 0x18208c,
2516 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); in gcc_sc7180_probe()
2517 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sc7180_probe()
2518 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sc7180_probe()
2525 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); in gcc_sc7180_probe()
2526 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); in gcc_sc7180_probe()
2527 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); in gcc_sc7180_probe()
2528 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sc7180_probe()