Lines Matching +full:0 +full:x50004
37 .offset = 0x0,
40 .enable_reg = 0x52018,
41 .enable_mask = BIT(0),
54 { 0x1, 2 },
59 .offset = 0x0,
76 .offset = 0x76000,
79 .enable_reg = 0x52018,
93 .offset = 0x1c000,
96 .enable_reg = 0x52018,
110 { P_BI_TCXO, 0 },
128 { P_BI_TCXO, 0 },
142 { P_BI_TCXO, 0 },
152 { P_BI_TCXO, 0 },
160 { P_BI_TCXO, 0 },
176 { P_BI_TCXO, 0 },
190 F(19200000, P_BI_TCXO, 1, 0, 0),
195 .cmd_rcgr = 0x48010,
196 .mnd_width = 0,
210 F(19200000, P_BI_TCXO, 1, 0, 0),
211 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
212 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
213 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
214 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
219 .cmd_rcgr = 0x64004,
233 .cmd_rcgr = 0x65004,
247 .cmd_rcgr = 0x66004,
261 F(9600000, P_BI_TCXO, 2, 0, 0),
262 F(19200000, P_BI_TCXO, 1, 0, 0),
267 .cmd_rcgr = 0x6b038,
281 .cmd_rcgr = 0x8d038,
295 .cmd_rcgr = 0x6038,
309 F(19200000, P_BI_TCXO, 1, 0, 0),
310 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
315 .cmd_rcgr = 0x6f014,
316 .mnd_width = 0,
329 F(9600000, P_BI_TCXO, 2, 0, 0),
330 F(19200000, P_BI_TCXO, 1, 0, 0),
331 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
336 .cmd_rcgr = 0x33010,
337 .mnd_width = 0,
352 F(19200000, P_BI_TCXO, 1, 0, 0),
356 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
358 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
361 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
365 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
377 .cmd_rcgr = 0x17010,
393 .cmd_rcgr = 0x17140,
404 F(19200000, P_BI_TCXO, 1, 0, 0),
408 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
410 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
413 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
425 .cmd_rcgr = 0x17270,
441 .cmd_rcgr = 0x173a0,
457 .cmd_rcgr = 0x174d0,
473 .cmd_rcgr = 0x17600,
489 .cmd_rcgr = 0x17730,
505 .cmd_rcgr = 0x17860,
521 .cmd_rcgr = 0x18010,
537 .cmd_rcgr = 0x18140,
553 .cmd_rcgr = 0x18270,
569 .cmd_rcgr = 0x183a0,
585 .cmd_rcgr = 0x184d0,
601 .cmd_rcgr = 0x18600,
617 .cmd_rcgr = 0x1e010,
633 .cmd_rcgr = 0x1e140,
649 .cmd_rcgr = 0x1e270,
665 .cmd_rcgr = 0x1e3a0,
681 .cmd_rcgr = 0x1e4d0,
697 .cmd_rcgr = 0x1e600,
707 F(19200000, P_BI_TCXO, 1, 0, 0),
708 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
709 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
710 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
711 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
716 .cmd_rcgr = 0x1400c,
732 F(19200000, P_BI_TCXO, 1, 0, 0),
733 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
734 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
735 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
740 .cmd_rcgr = 0x1600c,
759 .cmd_rcgr = 0x36010,
773 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
774 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
775 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
776 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
781 .cmd_rcgr = 0x75024,
795 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
796 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
797 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
798 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
803 .cmd_rcgr = 0x7506c,
804 .mnd_width = 0,
817 F(19200000, P_BI_TCXO, 1, 0, 0),
822 .cmd_rcgr = 0x750a0,
823 .mnd_width = 0,
836 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
837 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
838 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
843 .cmd_rcgr = 0x75084,
844 .mnd_width = 0,
857 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
858 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
859 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
860 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
861 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
866 .cmd_rcgr = 0x77024,
880 .cmd_rcgr = 0x7706c,
881 .mnd_width = 0,
894 .cmd_rcgr = 0x770a0,
895 .mnd_width = 0,
908 .cmd_rcgr = 0x77084,
909 .mnd_width = 0,
922 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
923 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
924 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
925 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
926 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
931 .cmd_rcgr = 0xf020,
945 .cmd_rcgr = 0xf038,
946 .mnd_width = 0,
959 .cmd_rcgr = 0x10020,
973 .cmd_rcgr = 0x10038,
974 .mnd_width = 0,
987 .cmd_rcgr = 0xf064,
988 .mnd_width = 0,
1001 .cmd_rcgr = 0x10064,
1002 .mnd_width = 0,
1015 .reg = 0x48028,
1016 .shift = 0,
1030 .reg = 0xf050,
1031 .shift = 0,
1045 .reg = 0x10050,
1046 .shift = 0,
1060 .halt_reg = 0x9000c,
1063 .enable_reg = 0x9000c,
1064 .enable_mask = BIT(0),
1073 .halt_reg = 0x750cc,
1075 .hwcg_reg = 0x750cc,
1078 .enable_reg = 0x750cc,
1079 .enable_mask = BIT(0),
1093 .halt_reg = 0x770cc,
1095 .hwcg_reg = 0x770cc,
1098 .enable_reg = 0x770cc,
1099 .enable_mask = BIT(0),
1113 .halt_reg = 0xf080,
1116 .enable_reg = 0xf080,
1117 .enable_mask = BIT(0),
1131 .halt_reg = 0x10080,
1134 .enable_reg = 0x10080,
1135 .enable_mask = BIT(0),
1149 .halt_reg = 0x38004,
1151 .hwcg_reg = 0x38004,
1154 .enable_reg = 0x52000,
1164 .halt_reg = 0xb02c,
1167 .enable_reg = 0xb02c,
1168 .enable_mask = BIT(0),
1177 .halt_reg = 0xb030,
1180 .enable_reg = 0xb030,
1181 .enable_mask = BIT(0),
1190 .halt_reg = 0xb040,
1193 .enable_reg = 0xb040,
1194 .enable_mask = BIT(0),
1203 .halt_reg = 0xf07c,
1206 .enable_reg = 0xf07c,
1207 .enable_mask = BIT(0),
1221 .halt_reg = 0x1007c,
1224 .enable_reg = 0x1007c,
1225 .enable_mask = BIT(0),
1239 .halt_reg = 0x48000,
1242 .enable_reg = 0x52000,
1257 .halt_reg = 0x48004,
1260 .enable_reg = 0x48004,
1261 .enable_mask = BIT(0),
1270 .halt_reg = 0x71154,
1273 .enable_reg = 0x71154,
1274 .enable_mask = BIT(0),
1283 .halt_reg = 0x8d058,
1286 .enable_reg = 0x8d058,
1287 .enable_mask = BIT(0),
1296 .halt_reg = 0xb034,
1299 .enable_reg = 0xb034,
1300 .enable_mask = BIT(0),
1309 .halt_reg = 0xb038,
1312 .enable_reg = 0xb038,
1313 .enable_mask = BIT(0),
1322 .halt_reg = 0xb044,
1325 .enable_reg = 0xb044,
1326 .enable_mask = BIT(0),
1335 .halt_reg = 0x64000,
1338 .enable_reg = 0x64000,
1339 .enable_mask = BIT(0),
1353 .halt_reg = 0x65000,
1356 .enable_reg = 0x65000,
1357 .enable_mask = BIT(0),
1371 .halt_reg = 0x66000,
1374 .enable_reg = 0x66000,
1375 .enable_mask = BIT(0),
1391 .enable_reg = 0x52000,
1408 .enable_reg = 0x52000,
1423 .halt_reg = 0x8c014,
1426 .enable_reg = 0x8c014,
1427 .enable_mask = BIT(0),
1436 .halt_reg = 0x7100c,
1439 .enable_reg = 0x7100c,
1440 .enable_mask = BIT(0),
1449 .halt_reg = 0x71018,
1452 .enable_reg = 0x71018,
1453 .enable_mask = BIT(0),
1462 .halt_reg = 0x4d008,
1465 .enable_reg = 0x4d008,
1466 .enable_mask = BIT(0),
1475 .halt_reg = 0x73008,
1478 .enable_reg = 0x73008,
1479 .enable_mask = BIT(0),
1488 .halt_reg = 0x73004,
1491 .enable_reg = 0x73004,
1492 .enable_mask = BIT(0),
1501 .halt_reg = 0x4d004,
1503 .hwcg_reg = 0x4d004,
1506 .enable_reg = 0x4d004,
1507 .enable_mask = BIT(0),
1516 .halt_reg = 0x4d00c,
1519 .enable_reg = 0x4d00c,
1520 .enable_mask = BIT(0),
1531 .enable_reg = 0x52000,
1548 .enable_reg = 0x52000,
1563 .halt_reg = 0x6f02c,
1566 .enable_reg = 0x6f02c,
1567 .enable_mask = BIT(0),
1581 .halt_reg = 0x6f030,
1584 .enable_reg = 0x6f030,
1585 .enable_mask = BIT(0),
1599 .halt_reg = 0x6f034,
1602 .enable_reg = 0x6f034,
1603 .enable_mask = BIT(0),
1617 .halt_reg = 0x6b028,
1620 .enable_reg = 0x52008,
1635 .halt_reg = 0x6b024,
1637 .hwcg_reg = 0x6b024,
1640 .enable_reg = 0x52008,
1650 .halt_reg = 0x6b01c,
1653 .enable_reg = 0x52008,
1663 .halt_reg = 0x6b02c,
1666 .enable_reg = 0x52008,
1676 .halt_reg = 0x6b014,
1678 .hwcg_reg = 0x6b014,
1681 .enable_reg = 0x52008,
1682 .enable_mask = BIT(0),
1691 .halt_reg = 0x6b010,
1694 .enable_reg = 0x52008,
1704 .halt_reg = 0x8d028,
1707 .enable_reg = 0x52000,
1722 .halt_reg = 0x8d024,
1724 .hwcg_reg = 0x8d024,
1727 .enable_reg = 0x52000,
1737 .halt_reg = 0x8d01c,
1740 .enable_reg = 0x52000,
1750 .halt_reg = 0x8d02c,
1753 .enable_reg = 0x52000,
1763 .halt_reg = 0x8d014,
1765 .hwcg_reg = 0x8d014,
1768 .enable_reg = 0x52000,
1778 .halt_reg = 0x8d010,
1781 .enable_reg = 0x52000,
1791 .halt_reg = 0x6028,
1794 .enable_reg = 0x52010,
1809 .halt_reg = 0x6024,
1811 .hwcg_reg = 0x6024,
1814 .enable_reg = 0x52010,
1824 .halt_reg = 0x601c,
1827 .enable_reg = 0x52010,
1837 .halt_reg = 0x602c,
1840 .enable_reg = 0x52010,
1850 .halt_reg = 0x6014,
1852 .hwcg_reg = 0x6014,
1855 .enable_reg = 0x52010,
1865 .halt_reg = 0x6010,
1868 .enable_reg = 0x52010,
1878 .halt_reg = 0x8c00c,
1881 .enable_reg = 0x8c00c,
1882 .enable_mask = BIT(0),
1891 .halt_reg = 0x6f004,
1894 .enable_reg = 0x6f004,
1895 .enable_mask = BIT(0),
1909 .halt_reg = 0x8c004,
1912 .enable_reg = 0x8c004,
1913 .enable_mask = BIT(0),
1922 .halt_reg = 0x8c008,
1925 .enable_reg = 0x8c008,
1926 .enable_mask = BIT(0),
1935 .halt_reg = 0x3300c,
1938 .enable_reg = 0x3300c,
1939 .enable_mask = BIT(0),
1953 .halt_reg = 0x33004,
1955 .hwcg_reg = 0x33004,
1958 .enable_reg = 0x33004,
1959 .enable_mask = BIT(0),
1968 .halt_reg = 0x33008,
1971 .enable_reg = 0x33008,
1972 .enable_mask = BIT(0),
1981 .halt_reg = 0x34004,
1984 .enable_reg = 0x52000,
1994 .halt_reg = 0xb018,
1996 .hwcg_reg = 0xb018,
1999 .enable_reg = 0xb018,
2000 .enable_mask = BIT(0),
2009 .halt_reg = 0xb01c,
2011 .hwcg_reg = 0xb01c,
2014 .enable_reg = 0xb01c,
2015 .enable_mask = BIT(0),
2024 .halt_reg = 0xb020,
2026 .hwcg_reg = 0xb020,
2029 .enable_reg = 0xb020,
2030 .enable_mask = BIT(0),
2039 .halt_reg = 0xb010,
2041 .hwcg_reg = 0xb010,
2044 .enable_reg = 0xb010,
2045 .enable_mask = BIT(0),
2054 .halt_reg = 0xb014,
2056 .hwcg_reg = 0xb014,
2059 .enable_reg = 0xb014,
2060 .enable_mask = BIT(0),
2069 .halt_reg = 0x23008,
2072 .enable_reg = 0x52008,
2082 .halt_reg = 0x23000,
2085 .enable_reg = 0x52008,
2095 .halt_reg = 0x1700c,
2098 .enable_reg = 0x52008,
2113 .halt_reg = 0x1713c,
2116 .enable_reg = 0x52008,
2131 .halt_reg = 0x1726c,
2134 .enable_reg = 0x52008,
2149 .halt_reg = 0x1739c,
2152 .enable_reg = 0x52008,
2167 .halt_reg = 0x174cc,
2170 .enable_reg = 0x52008,
2185 .halt_reg = 0x175fc,
2188 .enable_reg = 0x52008,
2203 .halt_reg = 0x1772c,
2206 .enable_reg = 0x52008,
2221 .halt_reg = 0x1785c,
2224 .enable_reg = 0x52008,
2239 .halt_reg = 0x23140,
2242 .enable_reg = 0x52008,
2252 .halt_reg = 0x23138,
2255 .enable_reg = 0x52008,
2265 .halt_reg = 0x1800c,
2268 .enable_reg = 0x52008,
2283 .halt_reg = 0x1813c,
2286 .enable_reg = 0x52008,
2301 .halt_reg = 0x1826c,
2304 .enable_reg = 0x52008,
2319 .halt_reg = 0x1839c,
2322 .enable_reg = 0x52008,
2337 .halt_reg = 0x184cc,
2340 .enable_reg = 0x52008,
2355 .halt_reg = 0x185fc,
2358 .enable_reg = 0x52008,
2373 .halt_reg = 0x23278,
2376 .enable_reg = 0x52010,
2386 .halt_reg = 0x23270,
2389 .enable_reg = 0x52010,
2390 .enable_mask = BIT(0),
2399 .halt_reg = 0x1e00c,
2402 .enable_reg = 0x52010,
2417 .halt_reg = 0x1e13c,
2420 .enable_reg = 0x52010,
2435 .halt_reg = 0x1e26c,
2438 .enable_reg = 0x52010,
2453 .halt_reg = 0x1e39c,
2456 .enable_reg = 0x52010,
2471 .halt_reg = 0x1e4cc,
2474 .enable_reg = 0x52010,
2489 .halt_reg = 0x1e5fc,
2492 .enable_reg = 0x52010,
2507 .halt_reg = 0x17004,
2510 .enable_reg = 0x52008,
2520 .halt_reg = 0x17008,
2522 .hwcg_reg = 0x17008,
2525 .enable_reg = 0x52008,
2535 .halt_reg = 0x18004,
2538 .enable_reg = 0x52008,
2548 .halt_reg = 0x18008,
2550 .hwcg_reg = 0x18008,
2553 .enable_reg = 0x52008,
2563 .halt_reg = 0x1e004,
2566 .enable_reg = 0x52010,
2576 .halt_reg = 0x1e008,
2578 .hwcg_reg = 0x1e008,
2581 .enable_reg = 0x52010,
2591 .halt_reg = 0x14008,
2594 .enable_reg = 0x14008,
2595 .enable_mask = BIT(0),
2604 .halt_reg = 0x14004,
2607 .enable_reg = 0x14004,
2608 .enable_mask = BIT(0),
2622 .halt_reg = 0x16008,
2625 .enable_reg = 0x16008,
2626 .enable_mask = BIT(0),
2635 .halt_reg = 0x16004,
2638 .enable_reg = 0x16004,
2639 .enable_mask = BIT(0),
2653 .halt_reg = 0x36004,
2656 .enable_reg = 0x36004,
2657 .enable_mask = BIT(0),
2666 .halt_reg = 0x3600c,
2669 .enable_reg = 0x3600c,
2670 .enable_mask = BIT(0),
2679 .halt_reg = 0x36008,
2682 .enable_reg = 0x36008,
2683 .enable_mask = BIT(0),
2697 .halt_reg = 0x8c000,
2700 .enable_reg = 0x8c000,
2701 .enable_mask = BIT(0),
2710 .halt_reg = 0x75018,
2712 .hwcg_reg = 0x75018,
2715 .enable_reg = 0x75018,
2716 .enable_mask = BIT(0),
2725 .halt_reg = 0x75010,
2727 .hwcg_reg = 0x75010,
2730 .enable_reg = 0x75010,
2731 .enable_mask = BIT(0),
2745 .halt_reg = 0x75064,
2747 .hwcg_reg = 0x75064,
2750 .enable_reg = 0x75064,
2751 .enable_mask = BIT(0),
2765 .halt_reg = 0x7509c,
2767 .hwcg_reg = 0x7509c,
2770 .enable_reg = 0x7509c,
2771 .enable_mask = BIT(0),
2785 .halt_reg = 0x75020,
2788 .enable_reg = 0x75020,
2789 .enable_mask = BIT(0),
2798 .halt_reg = 0x750b8,
2801 .enable_reg = 0x750b8,
2802 .enable_mask = BIT(0),
2811 .halt_reg = 0x7501c,
2814 .enable_reg = 0x7501c,
2815 .enable_mask = BIT(0),
2824 .halt_reg = 0x7505c,
2826 .hwcg_reg = 0x7505c,
2829 .enable_reg = 0x7505c,
2830 .enable_mask = BIT(0),
2844 .halt_reg = 0x77018,
2846 .hwcg_reg = 0x77018,
2849 .enable_reg = 0x77018,
2850 .enable_mask = BIT(0),
2859 .halt_reg = 0x77010,
2861 .hwcg_reg = 0x77010,
2864 .enable_reg = 0x77010,
2865 .enable_mask = BIT(0),
2879 .halt_reg = 0x77064,
2881 .hwcg_reg = 0x77064,
2884 .enable_reg = 0x77064,
2885 .enable_mask = BIT(0),
2899 .halt_reg = 0x7709c,
2901 .hwcg_reg = 0x7709c,
2904 .enable_reg = 0x7709c,
2905 .enable_mask = BIT(0),
2919 .halt_reg = 0x77020,
2922 .enable_reg = 0x77020,
2923 .enable_mask = BIT(0),
2932 .halt_reg = 0x770b8,
2935 .enable_reg = 0x770b8,
2936 .enable_mask = BIT(0),
2945 .halt_reg = 0x7701c,
2948 .enable_reg = 0x7701c,
2949 .enable_mask = BIT(0),
2958 .halt_reg = 0x7705c,
2960 .hwcg_reg = 0x7705c,
2963 .enable_reg = 0x7705c,
2964 .enable_mask = BIT(0),
2978 .halt_reg = 0xf010,
2981 .enable_reg = 0xf010,
2982 .enable_mask = BIT(0),
2996 .halt_reg = 0xf01c,
2999 .enable_reg = 0xf01c,
3000 .enable_mask = BIT(0),
3015 .halt_reg = 0xf018,
3018 .enable_reg = 0xf018,
3019 .enable_mask = BIT(0),
3028 .halt_reg = 0x10010,
3031 .enable_reg = 0x10010,
3032 .enable_mask = BIT(0),
3046 .halt_reg = 0x1001c,
3049 .enable_reg = 0x1001c,
3050 .enable_mask = BIT(0),
3065 .halt_reg = 0x10018,
3068 .enable_reg = 0x10018,
3069 .enable_mask = BIT(0),
3078 .halt_reg = 0xf054,
3081 .enable_reg = 0xf054,
3082 .enable_mask = BIT(0),
3096 .halt_reg = 0xf058,
3099 .enable_reg = 0xf058,
3100 .enable_mask = BIT(0),
3114 .halt_reg = 0xf05c,
3117 .enable_reg = 0xf05c,
3118 .enable_mask = BIT(0),
3127 .halt_reg = 0x8c010,
3130 .enable_reg = 0x8c010,
3131 .enable_mask = BIT(0),
3140 .halt_reg = 0x10054,
3143 .enable_reg = 0x10054,
3144 .enable_mask = BIT(0),
3158 .halt_reg = 0x10058,
3161 .enable_reg = 0x10058,
3162 .enable_mask = BIT(0),
3176 .halt_reg = 0x1005c,
3179 .enable_reg = 0x1005c,
3180 .enable_mask = BIT(0),
3189 .halt_reg = 0xb024,
3192 .enable_reg = 0xb024,
3193 .enable_mask = BIT(0),
3202 .halt_reg = 0xb028,
3205 .enable_reg = 0xb028,
3206 .enable_mask = BIT(0),
3215 .halt_reg = 0xb03c,
3218 .enable_reg = 0xb03c,
3219 .enable_mask = BIT(0),
3228 .gdscr = 0x6b004,
3236 .gdscr = 0x8d004,
3244 .gdscr = 0x6004,
3252 .gdscr = 0x75004,
3260 .gdscr = 0x77004,
3268 .gdscr = 0xf004,
3276 .gdscr = 0x10004,
3284 .gdscr = 0x7d050,
3293 .gdscr = 0x7d058,
3302 .gdscr = 0x7d054,
3311 .gdscr = 0x7d06c,
3539 [GCC_GPU_BCR] = { 0x71000 },
3540 [GCC_MMSS_BCR] = { 0xb000 },
3541 [GCC_NPU_BWMON_BCR] = { 0x73000 },
3542 [GCC_NPU_BCR] = { 0x4d000 },
3543 [GCC_PCIE_0_BCR] = { 0x6b000 },
3544 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3545 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3546 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3547 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3548 [GCC_PCIE_1_BCR] = { 0x8d000 },
3549 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3550 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3551 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3552 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
3553 [GCC_PCIE_2_BCR] = { 0x6000 },
3554 [GCC_PCIE_2_LINK_DOWN_BCR] = { 0x1f014 },
3555 [GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x1f020 },
3556 [GCC_PCIE_2_PHY_BCR] = { 0x1f01c },
3557 [GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x1f028 },
3558 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3559 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3560 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3561 [GCC_PDM_BCR] = { 0x33000 },
3562 [GCC_PRNG_BCR] = { 0x34000 },
3563 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3564 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3565 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3566 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3567 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3568 [GCC_SDCC2_BCR] = { 0x14000 },
3569 [GCC_SDCC4_BCR] = { 0x16000 },
3570 [GCC_TSIF_BCR] = { 0x36000 },
3571 [GCC_UFS_CARD_BCR] = { 0x75000 },
3572 [GCC_UFS_PHY_BCR] = { 0x77000 },
3573 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3574 [GCC_USB30_SEC_BCR] = { 0x10000 },
3575 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3576 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3577 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3578 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3579 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3580 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3581 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3582 [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, 2 },
3583 [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, 2 },
3613 .max_register = 0x9c100,
3646 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sm8250_probe()
3647 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sm8250_probe()
3655 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); in gcc_sm8250_probe()
3656 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); in gcc_sm8250_probe()
3657 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); in gcc_sm8250_probe()
3658 regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); in gcc_sm8250_probe()
3659 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); in gcc_sm8250_probe()
3660 regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); in gcc_sm8250_probe()