1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2014  Ulrich Hecht
8 #include <linux/clk-provider.h>
24 #define CPG_CKSCR	0xc0
25 #define CPG_FRQCRA	0x00
26 #define CPG_FRQCRB	0x04
27 #define CPG_FRQCRC	0xe0
28 #define CPG_PLL0CR	0xd8
29 #define CPG_PLL1CR	0x28
30 #define CPG_PLL2CR	0x2c
31 #define CPG_PLL2HCR	0xe4
32 #define CPG_PLL2SCR	0xf4
34 #define CLK_ENABLE_ON_INIT BIT(0)
37 	const char *name;  member
62 			     const char *name)  in r8a73a4_cpg_register_clock()  argument
71 	if (!strcmp(name, "main")) {  in r8a73a4_cpg_register_clock()
72 		u32 ckscr = readl(cpg->reg + CPG_CKSCR);  in r8a73a4_cpg_register_clock()
90 	} else if (!strcmp(name, "pll0")) {  in r8a73a4_cpg_register_clock()
96 		u32 value = readl(cpg->reg + CPG_PLL0CR);  in r8a73a4_cpg_register_clock()
102 	} else if (!strcmp(name, "pll1")) {  in r8a73a4_cpg_register_clock()
103 		u32 value = readl(cpg->reg + CPG_PLL1CR);  in r8a73a4_cpg_register_clock()
110 	} else if (!strncmp(name, "pll2", 4)) {  in r8a73a4_cpg_register_clock()
113 		switch (name[4]) {  in r8a73a4_cpg_register_clock()
124 			return ERR_PTR(-EINVAL);  in r8a73a4_cpg_register_clock()
126 		value = readl(cpg->reg + cr);  in r8a73a4_cpg_register_clock()
148 				name);  in r8a73a4_cpg_register_clock()
149 			return ERR_PTR(-EINVAL);  in r8a73a4_cpg_register_clock()
153 	} else if (!strcmp(name, "z") || !strcmp(name, "z2")) {  in r8a73a4_cpg_register_clock()
157 		if (name[1] == '2') {  in r8a73a4_cpg_register_clock()
162 		mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);  in r8a73a4_cpg_register_clock()
164 		struct div4_clk *c;  in r8a73a4_cpg_register_clock()  local
166 		for (c = div4_clks; c->name; c++) {  in r8a73a4_cpg_register_clock()
167 			if (!strcmp(name, c->name))  in r8a73a4_cpg_register_clock()
170 		if (!c->name)  in r8a73a4_cpg_register_clock()
171 			return ERR_PTR(-EINVAL);  in r8a73a4_cpg_register_clock()
175 		reg = c->reg;  in r8a73a4_cpg_register_clock()
176 		shift = c->shift;  in r8a73a4_cpg_register_clock()
180 		return clk_register_fixed_factor(NULL, name, parent_name, 0,  in r8a73a4_cpg_register_clock()
183 		return clk_register_divider_table(NULL, name, parent_name, 0,  in r8a73a4_cpg_register_clock()
184 						  cpg->reg + reg, shift, 4, 0,  in r8a73a4_cpg_register_clock()
185 						  table, &cpg->lock);  in r8a73a4_cpg_register_clock()
196 	num_clks = of_property_count_strings(np, "clock-output-names");  in r8a73a4_cpg_clocks_init()
211 	spin_lock_init(&cpg->lock);  in r8a73a4_cpg_clocks_init()
213 	cpg->data.clks = clks;  in r8a73a4_cpg_clocks_init()
214 	cpg->data.clk_num = num_clks;  in r8a73a4_cpg_clocks_init()
216 	cpg->reg = of_iomap(np, 0);  in r8a73a4_cpg_clocks_init()
217 	if (WARN_ON(cpg->reg == NULL))  in r8a73a4_cpg_clocks_init()
221 		const char *name;  in r8a73a4_cpg_clocks_init()  local
224 		of_property_read_string_index(np, "clock-output-names", i,  in r8a73a4_cpg_clocks_init()
225 					      &name);  in r8a73a4_cpg_clocks_init()
227 		clk = r8a73a4_cpg_register_clock(np, cpg, name);  in r8a73a4_cpg_clocks_init()
230 			       __func__, np, name, PTR_ERR(clk));  in r8a73a4_cpg_clocks_init()
232 			cpg->data.clks[i] = clk;  in r8a73a4_cpg_clocks_init()
235 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);  in r8a73a4_cpg_clocks_init()
237 CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",